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    Device of the phase-locked loop type for demodulating a frequency-modulated signal
    101.
    发明授权
    Device of the phase-locked loop type for demodulating a frequency-modulated signal 失效
    用于解调频率调制信号的锁相环类型的装置

    公开(公告)号：US5786726A

    公开(公告)日：1998-07-28

    申请号：US741166

    申请日：1996-10-29

    Applicant: Pascal Lemasson

    Inventor： Pascal Lemasson

    IPC: H04N5/455 ,  H03B1/00 ,  H03B5/12 ,  H03D3/02 ,  H03D3/24 ,  H03L7/099 ,  H03D3/00 ,  H03B5/08 ,  H03H11/48

    CPC classification number: H03D3/241 ,  H03B5/1209 ,  H03B5/1231 ,  H03B5/1243 ,  H03B2200/0036 ,  H03B2200/0092 ,  H03B2201/02 ,  H03D2200/0019

    Abstract: Device of the phase-locked loop type for demodulating a frequency-modulated signal. Device for frequency demodulation, using a phase-locked loop. According to the invention, for linearizing the variation of the frequency of a local oscillator (11) as a function of its control signal (Vb), a variable capacitance (Cv) is formed by an electronic module (20) which supplies the equivalent of a capacitance whose variation as a function of the control voltage (Vb) has a linearity deviation which is established for compensating the linearity deviation of the frequency of the oscillator as a function of the value of the capacitance (Cv).

    Abstract translation: 用于解调频率调制信号的锁相环类型的装置。 用于频率解调的装置，使用锁相环。 根据本发明，为了将本地振荡器（11）的频率变化作为其控制信号（Vb）的函数进行线性化，可变电容（Cv）由电子模块（20）形成，电子模块（20）提供相当于 作为控制电压（Vb）的函数的变化的电容具有作为用于补偿作为电容值（Cv）的函数的振荡器的频率的线性偏差而建立的线性偏差。

    Voltage controlled oscillator and voltage controlled delay circuit
    102.
    发明授权
    Voltage controlled oscillator and voltage controlled delay circuit 失效
    压控振荡器和电压控制延迟电路

    公开(公告)号：US5767748A

    公开(公告)日：1998-06-16

    申请号：US796621

    申请日：1997-02-07

    Applicant: Takehiko Nakao

    Inventor： Takehiko Nakao

    IPC: H03K3/354 ,  H03B1/00 ,  H03B5/24 ,  H03F3/45 ,  H03K3/0231 ,  H03K3/03 ,  H03B5/00

    CPC classification number: H03B5/24 ,  H03K3/0231 ,  H03B2200/0028 ,  H03B2200/0082 ,  H03B2200/0088 ,  H03B2200/0092 ,  H03B2200/0098 ,  H03B2201/02

    Abstract: A voltage controlled oscillator is capable of rectilinearly changing an oscillation frequency over a wide range while keeping, to a fixed value, a signal amplitude of a ring oscillator using an differential amplifier by eliminating dependency of the signal amplitude upon a tail current. A load resistor section of each delay element is constructed of a variable resistor element for changing a differential output current flowing corresponding to variations in tail current, and a clamp circuit for fixing the amplitude of an output terminal of the delay element. A control voltage for changing the current of the former part is generated by the replica circuit of the delay element that is equivalent to an arrangement that the part, for fixing the amplitude of the output terminal of the delay element, of the load resistor of the delay element, is removed, and by a control circuit for equalizing a reference voltage for determining the amplitude of the output terminal of the delay element to an output voltage of the replica circuit.

    Abstract translation: 压控振荡器能够在宽范围内直线地改变振荡频率，同时通过消除信号幅度对尾电流的依赖性而将使用差分放大器的环形振荡器的信号振幅保持在固定值。 每个延迟元件的负载电阻器部分由用于改变对应于尾电流变化的差分输出电流的可变电阻器元件和用于固定延迟元件的输出端子的振幅的钳位电路构成。 用于改变前一部分的电流的控制电压由延迟元件的复制电路产生，该复制电路相当于用于固定延迟元件的输出端的振幅的部分， 延迟元件，以及用于将用于确定延迟元件的输出端子的幅度的参考电压与复制电路的输出电压相平衡的控制电路。

    Voltage controlled oscillator (VCO) frequency gain compensation circuit
    103.
    发明授权
    Voltage controlled oscillator (VCO) frequency gain compensation circuit 失效

    公开(公告)号：US5748048A

    公开(公告)日：1998-05-05

    申请号：US766389

    申请日：1996-12-12

    Applicant: Nathan Y. Moyal

    Inventor： Nathan Y. Moyal

    IPC: H03B1/00 ,  H03K3/0231 ,  H03L7/093 ,  H03L7/099 ,  H03B5/04

    CPC classification number: H03L7/0995 ,  H03K3/0231 ,  H03L7/093 ,  H03B2201/02 ,  H03L2207/05

    Abstract: A voltage controlled oscillator (VCO) having a current gain compensation circuit includes a control circuit portion for generating a frequency control signal, and a ring oscillator responsive to the frequency control signal for outputting the VCO output signal. The control circuit includes a control transistor responsive to input control voltage V.sub.control. Connected between the source terminal of the control transistor and ground is a resistive element in parallel with an N-channel field effect transistor and a P-channel field effect transistor, each configured to operate in saturation. The resistor, and the N-channel, and P-channel transistors provide parallel current paths which, collectively, form a control current that corresponds to the frequency control signal. As the voltage control signal V.sub.control increases beyond a predetermined level, the transistors conduct, and carry a current that is proportional to the square of the input control voltage V.sub.control. Accordingly, the magnitude of total control current is dominated by the transistor-provided component, and assumes a square relationship, with respect to the input control voltage. This square-law current-voltage gain characteristic compensates for the inversely mirrored frequency gain characteristic of the ring oscillator in order to attain a reduced frequency gain variation for the overall VCO, with respect to control voltage variations. This reduction in variation translates to a reduced variation in the frequency gain of the VCO with respect to temperature variations when the VCO is used in a phase locked loop (PLL) circuit.

    PLL circuit
    104.
    发明授权
    PLL circuit 失效
    PLL电路

    公开(公告)号：US5581584A

    公开(公告)日：1996-12-03

    申请号：US277951

    申请日：1994-07-20

    Applicant: Atsushi Inoue ,  Toshio Hata ,  Osamu Tamakoshi ,  Takayasu Komaki

    Inventor： Atsushi Inoue ,  Toshio Hata ,  Osamu Tamakoshi ,  Takayasu Komaki

    IPC: H03L7/06 ,  H03B1/00 ,  H03B7/02 ,  H03B7/06 ,  H03L7/099 ,  H03D3/24

    CPC classification number: H03B7/02 ,  H03L7/099 ,  H03B2201/02 ,  H03B7/06

    Abstract: A PLL circuit includes a PLLic formed into an integrated circuit; a loop filter for receiving an output signal from the PLLic; a voltage-controlled oscillator having an oscillation frequency which is controlled according to an output signal of the loop filter for applying a controlled oscillation output signal to the PLLic, the voltage-controlled oscillator including a resonator and a negative resistor circuit; wherein a buffer amplifier functioning as a part of the voltage-controlled oscillator is incorporated into the PLLic, and the resonator and the negative resistor circuit of the voltage-controlled oscillator are disposed outside of the PLLic.

    Abstract translation: PLL电路包括形成为集成电路的PLL; 用于接收来自PLL的输出信号的环路滤波器; 压控振荡器，其具有根据所述环路滤波器的输出信号控制的振荡频率，用于向所述PLL提供受控振荡输出信号，所述压控振荡器包括谐振器和负电阻电路; 其中用作压控振荡器的一部分的缓冲放大器被并入到PLL中，并且压控振荡器的谐振器和负电阻电路设置在PLL的外部。

    Voltage-controlled ring oscillator using complementary differential buffers for generating multiple phase signals
    105.
    发明授权
    Voltage-controlled ring oscillator using complementary differential buffers for generating multiple phase signals 失效
    使用互补差分缓冲器产生多相信号的压控环形振荡器

    公开(公告)号：US5239274A

    公开(公告)日：1993-08-24

    申请号：US888762

    申请日：1992-05-26

    Applicant: Kuang K. Chi

    Inventor： Kuang K. Chi

    IPC: H03B1/00 ,  H03B5/20 ,  H03B27/00 ,  H03K3/0231 ,  H03K3/03

    CPC classification number: H03B27/00 ,  H03B5/20 ,  H03K3/0231 ,  H03K3/0322 ,  H03B2200/0062 ,  H03B2201/02

    Abstract: Differential buffers are used in a voltage-controlled oscillator to provide pairs of complementary phase signals. The preferred arrangement includes a ring of the differential buffers. Each differential buffer has a current control input, and the current control inputs of the buffers are all connected to a control voltage input to simultaneously adjust the propagation delay of each of the buffers. In contrast to a conventional ring oscillator, which has an odd number of stages, a ring oscillator made of differential buffers can have an even number of buffers to provide a number of phases that is a multiple of four. The differential buffer preferably includes a pair of CMOS inverters sharing a common PMOS current sourcing transistor and a common NMOS current sinking transistor.

    Abstract translation: 差分缓冲器用于压控振荡器以提供成对的互补相位信号。 优选的布置包括差动缓冲器的环。 每个差分缓冲器具有电流控制输入，并且缓冲器的电流控制输入都连接到控制电压输入端以同时调节每个缓冲器的传播延迟。 与具有奇数级级的常规环形振荡器相比，由差分缓冲器构成的环形振荡器可以具有偶数个缓冲器，以提供多个相位的倍数为4。 差分缓冲器优选地包括共享公共PMOS电流源晶体管和公共NMOS电流吸收晶体管的一对CMOS反相器。

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