Abstract:
The circuit (2) is integrated in the CMOS technology, excepting for the resonant crystal (1). The device consists of several basic cells (Z1-Zn) with feedback resistances (R1-Rn). Each cell has two capacitors (C11,C21) connected in parallel with the crystal, two amplifying transistors (p11,n11) and two switching transistors (p21,n21). One capacitor (C11) is switched (S11) to the interconnected gate electrodes of the amplifiers, and the other capacitor (C21) is switched (S21) to the feedback resistance, by a control signal (I1) which is also inverted (5) for one switching transistor (p21), but not for the other (n21).
Abstract:
본원의실시예들은듀얼모드발진기및 다중위상발진기를개시한다. 듀얼모드발진기에서, 모드스위칭회로를사용하여두 개의동작모드사이의스위칭이구현되어, 서로상이한두 개의대역을갖는발진신호가획득될수 있다. 또한, 듀얼모드발진기는두 개의변압기결합발진기를포함하고, 임의의변압기결합발진기내의승압변압기는제1 MOS 트랜지스터의드레인전압스윙을승산한다음, 제2 MOS 트랜지스터의게이트에전압신호를인가하여, 발진기의공급전압을증가시키지않으면서더 큰게이트전압스윙이획득되고, 듀얼모드발진기의위상잡음성능이향상된다. 다중위상발진기에서, 다중듀얼모드변압기결합발진기는다중위상결합회로를통해연결되어뫼비우스루프를형성하여, 다중위상의발진신호가생성될수 있고, 전체발진기의위상잡음성능이향상될수 있다.
Abstract:
Digital adjustment of an oscillator is provided to adjust the oscillation frequency of the oscillator to perform the selective change of an oscillation frequency efficiently without the damping of the oscillator. Digital adjustment of an oscillator includes at least one pair of capacitors(C,C'), first field effect transistors(T1,T1'), a second field effect transistor(T2), and third field effect transistors(T3,T3'). The pair of capacitors have first terminals connected to the oscillator, and second terminals selectively connected to a first reference potential(vss) by the switching arrangement to integrate the capacitors with an oscillation circuit of the oscillator. The first field effect transistors individually connect the second terminals and the first reference potential. The second field effect transistor connects the second terminals to each other. The third field effect transistors individually connect the second terminals and a second reference potential(vdd) which is different from the first reference potential.
Abstract:
본 발명은 2개의 발진신호를 변환하여 공통의 단자로부터 출력하는 경우에, 발진신호의 감쇠를 적게 하기 위하여, 제 1 주파수대의 발진신호를 출력하는 제 1 발진 트랜지스터(11)와, 제 1 발진 트랜지스터(11)의 콜렉터에 전원을 공급하는 제 1 인덕터(12)와, 제 1 발진 트랜지스터(11)의 동작을 변환하는 제 1 스위치 소자(16)와, 제 2 주파수대의 발진신호를 출력하는 제 2 발진 트랜지스터(21)와, 제 2 발진 트랜지스터(21)의 콜렉터에 전원을 공급하는 제 2 인덕터(22)와, 제 2 발진 트랜지스터(21)의 동작을 변환하는 제 2 스위치 소자(26)와, 제 1 주파수대의 발진신호 또는 제 2 주파수대의 발진신호를 외부에 출력하는 출력단자(30)를 구비하고, 제 1 인덕터(12)와 출력단자(30)와의 사이에 제 1 스위치 소자(16)를 거쳐 삽입하고, 제 2 인덕터(22)와 출력단자(30)와의 사이에 제 2 스위치 소자(26)를 거쳐 삽입하였다.
Abstract:
The invention relates to a resonator circuit (100), the resonator circuit (100) comprising a transformer (101) comprising a primary winding (103) and a secondary winding (105), wherein the primary winding (103) is inductively coupled with the secondary winding (105), a primary capacitor (107) being connected to the primary winding (103), the primary capacitor (107) and the primary winding (103) forming a primary circuit, and a secondary capacitor (109) being connected to the secondary winding (105), the secondary capacitor (109) and the secondary winding (105) forming a secondary circuit, wherein the resonator circuit (100) has a common mode resonance frequency at an excitation of the primary circuit in a common mode, wherein the resonator circuit (100) has a differential mode resonance frequency at an excitation of the primary circuit in a differential mode, and wherein the common mode resonance frequency is different from the differential mode resonance frequency.
Abstract:
An oscillator circuit may selectively switch between a normal mode and a low-power mode in response to a mode signal. During the normal mode, the oscillator circuit may employ a first amplifier configuration and a first capacitive loading to generate a high-accuracy clock signal having a relatively low frequency error. During the low power mode, the oscillator circuit may employ a second amplifier configuration and a second capacitive loading to generate a low-power clock signal using minimal power consumption. A compensation circuit may be used to offset a relatively high frequency error during the low-power mode.
Abstract:
An integrated circuit includes a delay lock loop (DLL) circuit that generates incremental delay line signals and a delay line output signal based on a received clock signal. A pulse-width modulation (PWM) control module generates a PWM control signal. A tunable circuit having variable capacitance is controlled based on the delay line output signal, the PWM control signal, and one of the incremental delay line signals.
Abstract:
An integrated VCO (4532) having an improved tuning range over process and temperature variations. There is therefore provided in a present embodiment of the invention an integrated VCO. The VCO comprises, a substrate, a VCO tuning control circuit (4535) responsive to a VCO state variable that is disposed upon the substrate, and a VCO disposed upon the substrate, having a tuning control voltage input falling within a VCO tuning range for adjusting a VCO frequency output, and having its tuning range adjusted by the tuning control circuit in response to the VCO state variable.
Abstract:
The invention provides a unique apparatus and method which varies the capacitance coupled to a circuit. In one embodiment, the variable capacitance comprises a unique variable capacitance array (402) with multiple capacitance modules (508, 540 and 550) which can be selectively enabled. Each capacitance module has a capacitive value (510, 542, 544, 552 and 556) and a corresponding parasitic capacitance. The invention provides high linearity, low spread, improves the response to power fluctuations by maintaining a consistent relationship between the capacitive value (510, 542, 544, 552 and 556) and the parasitic capacitance in each capacitance module (508, 540 and 550). For example, the invention can be used with devices to provide a linear variation of capacitance. In addition, the invention can be used to calibrate a wide range of devices.