公开(公告)号：US20160352347A1

公开(公告)日：2016-12-01

申请号：US15153711

申请日：2016-05-12

Applicant: ANALOG DEVICES, INC.

Inventor： PAUL R. FERNANDO ,  SUDARSHAN ANANDA NATARAJAN

IPC: H03M1/10 ,  H03M1/20 ,  H04N5/378 ,  H03M1/46

CPC classification number: H03M1/1009 ,  H03M1/0639 ,  H03M1/1061 ,  H03M1/201 ,  H03M1/466 ,  H03M1/468

Abstract: Disclosed herein are systems for calibrating an analog-to-digital converter (ADC) device, as well as related devices and methods. In some embodiments, a system for calibrating an ADC device may include an ADC device, wherein the ADC device includes an ADC and a dither source, and wherein the ADC device is to apply a set of calibration parameters to generate digital outputs. The system may also include calibration circuitry, coupled to the ADC device, to determine which of multiple sets of values of calibration parameters results in the digital outputs having the lowest amount of noise, and to cause the ADC device to apply the calibration parameters associated with the lowest noise.

Abstract translation: 本文公开了用于校准模数转换器（ADC）装置以及相关装置和方法的系统。 在一些实施例中，用于校准ADC器件的系统可以包括ADC器件，其中ADC器件包括ADC和抖动源，并且其中ADC器件将应用一组校准参数以产生数字输出。 该系统还可以包括耦合到ADC器件的校准电路，以确定校准参数的多组值中的哪一组导致具有最低噪声量的数字输出，并且使得ADC器件施加与 噪音最低

公开(公告)号：US09461665B1

公开(公告)日：2016-10-04

申请号：US14837049

申请日：2015-08-27

Applicant: Korea University Research and Business Foundation

Inventor： Chulwoo Kim ,  Sejin Park

IPC: H03M1/46 ,  H03M1/06

CPC classification number: H03M1/462 ,  H03M1/0607 ,  H03M1/201 ,  H03M1/468

Abstract: A Successive Approximated Register Analog-to-Digital Converter (“SARADC”) is provided that includes: a bootstrapping unit that receives and samples analog signals; and an Analog-to-Digital Conversion Unit (“ADCU”) that converts the analog signals into digital signals and outputs the digital signals. ADCU has a resolution increasing in response to an intentionally injected offset voltage. In this case, ADCU includes Capacitor Arrays (“CAs”) having: a differential structure each including reference voltage application capacitors having different capacitances and an Offset Voltage Injection Capacitor (“OVIC”); a delay cell that operates CAs in an asynchronous mode; Reference Transfer Switch Units (“RTSUs”) that apply a reference voltage to CAs; a comparator that compares output voltages of CAs; and Successive Approximated Register Logics (“SARLs”). SARLs control operations of RTSUs in response to an output signal of the comparator and perform control so that a reference voltage is applied to OVICs when the output of the comparator is abnormal.

Abstract translation: 提供了一种连续近似寄存器模数转换器（“SARADC”），其包括：自举单元，其接收和采样模拟信号; 以及将模拟信号转换为数字信号并输出​​数字信号的模数转换单元（“ADCU”）。 ADCU响应于有意注入的失调电压而具有增加的分辨率。 在这种情况下，ADCU包括具有：差分结构的电容阵列（“CA”），每个差分结构包括具有不同电容的参考电压施加电容器和偏移电压注入电容器（“OVIC”）; 以异步模式操作CA的延迟单元; 参考转换开关单元（“RTSU”），将参考电压应用于CA; 比较器，用于比较CA的输出电压; 和连续近似寄存器逻辑（“SARL”）。 SARL根据比较器的输出信号控制RTSU的操作，并执行控制，以便当比较器的输出异常时，将参考电压施加到OVIC。

公开(公告)号：US09413379B2

公开(公告)日：2016-08-09

申请号：US14690881

申请日：2015-04-20

Applicant: Samsung Electronics Co., Ltd. ,  IUCF-HYU (Industry-University Cooperation Foundation Hanyang University)

Inventor： Yun-Jung Kim ,  Jong-Boo Kim ,  Oh-Kyong Kwon

IPC: H03M1/12 ,  H03M1/46 ,  H03M1/20 ,  H03M1/80 ,  H03M1/00

CPC classification number: H03M1/468 ,  H03M1/00 ,  H03M1/12 ,  H03M1/123 ,  H03M1/201 ,  H03M1/804

Abstract: An analog-to-digital converter includes a digital-to-analog converter comprising a capacitor divider network comprising a plurality of dividing capacitors and a dummy capacitor. The digital-to-analog converter is configured to selectively apply an input voltage and a reference voltage to the dividing capacitors and to selectively apply the input voltage and a shift voltage to the dummy capacitor. The analog-to-digital converter further includes a comparison circuit configured to compare an output of the capacitor divider network and a common mode voltage and a shift voltage generator circuit configured to generate the shift voltage. The shift voltage generator circuit may be configured to vary the shift voltage for different samples of the input voltage. For example, the shift voltage generator circuit may be configured to change the shift voltage for succeeding samples by an amount corresponding to 1/(2^M) times the reference voltage to support 2^M oversampling of the input voltage.

Abstract translation: 模数转换器包括数模转换器，其包括包括多个分压电容器和虚拟电容器的电容分压网络。 数模转换器被配置为向分压电容器选择性地施加输入电压和参考电压，并且选择性地将输入电压和移位电压施加到虚拟电容器。 模数转换器还包括比较电路，其被配置为比较电容分压器网络的输出和共模电压，以及被配置为产生移位电压的移位电压发生器电路。 移位电压发生器电路可以被配置为改变输入电压的不同样本的移位电压。 例如，移位电压发生器电路可以被配置为将后续样本的移位电压改变相当于参考电压的1 /（2 ^ M）倍的量，以支持输入电压的2×M过采样。

公开(公告)号：US09401677B2

公开(公告)日：2016-07-26

申请号：US14831119

申请日：2015-08-20

Applicant: Augusto Ronchini Ximenes ,  Robert Bogdan Staszewski

Inventor： Augusto Ronchini Ximenes ,  Robert Bogdan Staszewski

IPC: H03B5/12 ,  H03B1/00 ,  H03K3/015 ,  G04F10/00 ,  H03L7/08 ,  H03M1/00 ,  H03L7/093 ,  H03M1/20 ,  H03L7/089 ,  H03L7/197 ,  H03K3/03

CPC classification number: H03B5/1265 ,  G04F10/005 ,  H03B1/00 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1296 ,  H03J2200/10 ,  H03K3/015 ,  H03K3/0315 ,  H03L7/0802 ,  H03L7/0893 ,  H03L7/093 ,  H03L7/1976 ,  H03L2207/50 ,  H03M1/002 ,  H03M1/201

Abstract: A novel and useful LC-tank digitally controlled oscillator (DCO) incorporating a split transformer configuration. The LC-tank oscillator exhibits a significant reduction in area such that it is comparable in size to conventional ring oscillators (ROs) while still retaining its salient features of excellent phase noise and low sensitivity to supply variations. The oscillator incorporates an ultra-compact split transformer topology that is less susceptible to common-mode electromagnetic interference than regular high-Q LC tanks which is highly desirable in SoC environments. The oscillator, together with a novel dc-coupled buffer, can be incorporated within a wide range of circuit applications, including clock generators and an all-digital phase-locked loop (ADPLL) intended for wireline applications.

Abstract translation: 一种新颖有用的LC-tank数字控制振荡器（DCO），其包含分离变压器配置。 LC-tank振荡器显示出显着的面积减小，使得它在尺寸上与常规的环形振荡器（RO）相当，同时仍然保持其显着的相位噪声特征以及对供应变化的低灵敏度。 该振荡器包含一个超紧凑型分离式变压器拓扑，它比常规高Q液相色谱箱容易受到共模电磁干扰的影响，这在SoC环境中是非常需要的。 该振荡器与一个新颖的直流耦合缓冲器可以并入广泛的电路应用中，包括时钟发生器和用于有线应用的全数字锁相环（ADPLL）。

公开(公告)号：US20160156366A1

公开(公告)日：2016-06-02

申请号：US14897854

申请日：2014-06-11

Applicant: IEE INTERNATIONAL ELECTRONICS & ENGINEERING S.A.

Inventor： Laurent LAMESCH

IPC: H03M1/20 ,  H03M1/12 ,  H03C3/02

CPC classification number: H03M1/20 ,  H03C3/02 ,  H03M1/124 ,  H03M1/201

Abstract: A capacitive sensing system operates according to a method which uses an ADC with a low resolution r, to produce a digital signal with a higher resolution R. The analog signal to be digitized is modulated with a triangular or saw-tooth modulating signal, so that a modulated analog signal is obtained, which is sampled with the ADC. Thereby, digital samples are produced. An average is taken over N (>1) successive digital samples. The triangular or saw-tooth signal is chosen to have a peak-to-peak amplitude corresponding at least approximately to an integer multiple L, with L≧1, of the quantization step size of the ADC. The saw-tooth or triangular signal, furthermore, has a number M, of periods per each sequence of N samples. M and N are chosen such that M>1 and M≠N and such that R=r*N/(k*gcd(N, M)*L), where gcd(M, N) is the greatest common divisor of N and M and where k=2 if the modulating signal is a saw-tooth signal and k=4 if the modulating signal is a triangular signal.

Abstract translation: 电容式感测系统根据使用具有低分辨率r的ADC的方法进行工作，以产生具有更高分辨率R的数字信号。要被数字化的模拟信号用三角形或锯齿调制信号调制，使得 得到一个调制的模拟信号，用ADC进行采样。 从而产生数字样本。 N（> 1）个连续数字样本的平均数。 三角形或锯齿状信号被选择为具有至少近似于ADC的量化步长的L≥1的整数倍L的峰峰值幅度。 此外，锯齿或三角形信号具有每个N个样本的每个序列的周期数M。 M和N被选择为使得M> 1且M≠N，并且使得R = r * N /（k * gcd（N，M）* L），其中gcd（M，N）是N的最大公约数 如果调制信号是锯齿信号，则k = 2，如果调制信号是三角形信号，则k = 4。

公开(公告)号：US20160056825A1

公开(公告)日：2016-02-25

申请号：US14831781

申请日：2015-08-20

Applicant: Gerasimos S. Vlachogiannakis ,  Augusto Ronchini Ximenes ,  Robert Bogdan Staszewski

Inventor： Gerasimos S. Vlachogiannakis ,  Augusto Ronchini Ximenes ,  Robert Bogdan Staszewski

IPC: H03L7/08 ,  G04F10/00 ,  H03M1/00

CPC classification number: H03B5/1265 ,  G04F10/005 ,  H03B1/00 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1296 ,  H03J2200/10 ,  H03K3/015 ,  H03K3/0315 ,  H03L7/0802 ,  H03L7/0893 ,  H03L7/093 ,  H03L7/1976 ,  H03L2207/50 ,  H03M1/002 ,  H03M1/201

Abstract: A novel and useful look-ahead time to digital converter (TDC) that is applied to an all digital phase locked loop (ADPLL) as the fractional phase error detector. The deterministic nature of the phase error during frequency/phase lock is exploited to achieve a reduction in power consumption of the TDC. The look-ahead TDC circuit is used to construct a cyclic DTC-TDC pair which functions to reduce fractional spurs of the output spectrum in near-integer channels by randomly rotating the cyclic DTC-TDC structure so that it starts from a different point every reference clock thereby averaging out the mismatch of the elements. Associated rotation and dithering methods are also presented. The ADPLL is achieved using the look-ahead TDC and/or cyclic DTC-TDC pair circuit.

Abstract translation: 数字转换器（TDC）的新颖有用的超前时间，适用于全数字锁相环（ADPLL）作为分数相位误差检测器。 利用频率/锁相期间相位误差的确定性来实现TDC功耗的降低。 先行TDC电路用于构造循环DTC-TDC对，其通过随机旋转循环DTC-TDC结构来减少近整数通道中的输出频谱的分数杂散，使其从每个参考的不同点开始 从而平均化元件的不匹配。 还提出了相关的旋转和抖动方法。 使用前瞻TDC和/或循环DTC-TDC对电路来实现ADPLL。

公开(公告)号：US20150303938A1

公开(公告)日：2015-10-22

申请号：US14690881

申请日：2015-04-20

Applicant: Samsung Electronics Co., Ltd. ,  IUCF-HYU (Industry-University Cooperation Foundation Hanyang University)

Inventor： Yun-Jung Kim ,  Jong-Boo Kim ,  Oh-Kyong Kwon

IPC: H03M1/46 ,  H03M1/12

CPC classification number: H03M1/468 ,  H03M1/00 ,  H03M1/12 ,  H03M1/123 ,  H03M1/201 ,  H03M1/804

Abstract: An analog-to-digital converter includes a digital-to-analog converter comprising a capacitor divider network comprising a plurality of dividing capacitors and a dummy capacitor. The digital-to-analog converter is configured to selectively apply an input voltage and a reference voltage to the dividing capacitors and to selectively apply the input voltage and a shift voltage to the dummy capacitor. The analog-to-digital converter further includes a comparison circuit configured to compare an output of the capacitor divider network and a common mode voltage and a shift voltage generator circuit configured to generate the shift voltage. The shift voltage generator circuit may be configured to vary the shift voltage for different samples of the input voltage. For example, the shift voltage generator circuit may be configured to change the shift voltage for succeeding samples by an amount corresponding to 1/(2̂M) times the reference voltage to support 2̂M oversampling of the input voltage.

Abstract translation: 模数转换器包括数模转换器，其包括包括多个分压电容器和虚拟电容器的电容分压网络。 数模转换器被配置为向分压电容器选择性地施加输入电压和参考电压，并且选择性地将输入电压和移位电压施加到虚拟电容器。 模数转换器还包括比较电路，其被配置为比较电容分压器网络的输出和共模电压，以及被配置为产生移位电压的移位电压发生器电路。 移位电压发生器电路可以被配置为改变输入电压的不同样本的移位电压。 例如，移位电压发生器电路可以被配置为将后续样本的移位电压改变相当于参考电压的1 /（2M）倍的量，以支持输入电压的2M过采样。

公开(公告)号：US09136861B1

公开(公告)日：2015-09-15

申请号：US14544851

申请日：2015-02-25

Applicant: Elta Systems Ltd.

Inventor： Baruch Fleishman

IPC: H03M1/20

CPC classification number: H03M1/201 ,  H04B1/0007 ,  H04B7/086

Abstract: A system and method for enhancing a dynamic range of a beamforming multi-channel digital receiver are described. The receiver comprises a plurality of receiving channels, each including an analog-to-digital converter configured for converting an analog input signal generated by antenna elements into a digital signal. A “spatial” dither signal is used to decorrelate the quantization noise of the analog-to-digital converters. A dither signal is generated and split into a predetermined number of coherent dithering signals. The method includes providing predetermined time delays to the coherent dithering signals, and adding the delayed coherent dithering signals to the input signals in each receiving channel, correspondingly, thereby creating a dither signal equivalent to a signal arriving from a certain specific direction out-of-field-of-view of the antenna array. Removing of the dither signal based on the direction of arrival, is implemented during beamforming signal processing, thus enhancing the dynamic range of electromagnetic signals arriving within a field-of-view of the antenna array.

公开(公告)号：US09007245B2

公开(公告)日：2015-04-14

申请号：US14445682

申请日：2014-07-29

Applicant: Renesas Electronics Corporation

Inventor： Keisuke Kimura ,  Yuichi Okuda ,  Hideo Nakane ,  Takaya Yamamoto ,  Tatsuji Matsuura

IPC: H03M1/20 ,  H03M3/00

CPC classification number: H03M3/49 ,  H03M1/201 ,  H03M3/328 ,  H03M3/332 ,  H03M3/43 ,  H03M3/438 ,  H03M3/486

Abstract: A semiconductor communication device reduces influence of noise that is produced by applying a dither signal. The semiconductor communication device includes a Delta-Sigma analog-to-digital converter that converts input analog signals to digital signals, a power detecting unit that detects signal power of the digital signals, a gain control unit that changes a gain setting of analog signals to be input to the Delta-Sigma analog-to-digital converter depending on the signal power of the digital signals, and a dither signal control unit that causes the Delta-Sigma analog-to-digital converter to selectively add the dither signal when the gain setting changes.

Abstract translation: 半导体通信设备减少通过应用抖动信号产生的噪声的影响。 该半导体通信装置包括将输入的模拟信号转换为数字信号的Delta-Sigma模数转换器，检测数字信号的信号功率的功率检测单元，将模拟信号的增益设定变更为 根据数字信号的信号功率输入到Delta-Sigma模数转换器;以及抖动信号控制单元，其使Delta-Sigma模数转换器在增益时选择性地添加抖动信号 设置更改。

公开(公告)号：US20140139363A1

公开(公告)日：2014-05-22

申请号：US13681371

申请日：2012-11-19

Applicant: Western Digital Technologies, Inc.

Inventor： George J. BENNETT

IPC: H03M1/20 ,  H03M1/12

CPC classification number: H03M1/201 ,  H03L7/0891 ,  H03L7/093 ,  H03M1/12 ,  H03M1/504

Abstract: An analog-to-digital converter is disclosed comprising a resonant oscillator comprising an input operable to receive an analog input signal and an output operable to output an oscillating signal. A DC offset detector detects a DC offset in the oscillating signal caused by the analog input signal, wherein the DC offset is converted into a digital output signal representing the analog input signal.

Abstract translation: 公开了一种模拟 - 数字转换器，其包括谐振振荡器，其包括可操作以接收模拟输入信号的输入和可操作以输出振荡信号的输出。 DC偏移检测器检测由模拟输入信号引起的振荡信号中的DC偏移，其中DC偏移被转换成表示模拟输入信号的数字输出信号。