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    Processor for executing switch and translate instructions requiring wide operands
    111.
    发明申请
    Processor for executing switch and translate instructions requiring wide operands 有权
    用于执行切换和转换需要广泛操作数的指令的处理器

    公开(公告)号：US20080189512A1

    公开(公告)日：2008-08-07

    申请号：US11982171

    申请日：2007-10-31

    Applicant: Craig Hansen ,  John Moussouris ,  Alexia Massalin

    Inventor： Craig Hansen ,  John Moussouris ,  Alexia Massalin

    IPC: G06F9/00

    CPC classification number: G06F12/02 ,  G06F9/30007 ,  G06F9/30014 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/30167 ,  G06F9/383 ,  G06F9/3861 ,  G06F9/3885 ,  G06F9/4484 ,  G06F9/45533

    Abstract: A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path width of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width and accessible number of general purpose registers.

    Abstract translation: 一种可编程处理器和方法，用于通过将至少两个源操作数或源和结果操作数扩展到大于通用寄存器或数据路径宽度的宽度的宽度来提高处理器的性能。 本发明通过使用通用寄存器的内容来指定可以读取或写入数据的多个数据路径宽度的存储器地址，并且基本上大于处理器的数据路径宽度的操作数，以及 操作数的大小和形状。 此外，描述了用于实现这些指令的几个指令和装置，其如果操作数不限于通用寄存器的宽度和可访问数量，则获得性能优点。

    Configurable cache allowing cache-type and buffer-type access
    116.
    再颁专利
    Configurable cache allowing cache-type and buffer-type access 有权
    可配置缓存允许缓存类型和缓冲区类型访问

    公开(公告)号：USRE39500E1

    公开(公告)日：2007-02-27

    申请号：US10901482

    申请日：2004-07-29

    Applicant: Craig C. Hansen

    Inventor： Craig C. Hansen

    IPC: G06F12/02

    CPC classification number: G06F12/0284 ,  G06F12/1045 ,  G06F12/1491

    Abstract: A virtual memory system including a local-to-global virtual address translator for translating local virtual addresses having associated task specific address spaces into global virtual addresses corresponding to an address space associated with multiple tasks, and a global virtual-to-physical address translator for translating global virtual addresses to physical addresses. Protection information is provided by each of the local virtual-to-global virtual address translator, the global virtual-to-physical address translator, the cache tag storage, or a protection information buffer depending on whether a cache hit or miss occurs during a given data or instruction access. The cache is configurable such that it can be configured into a buffer portion or a cache portion for faster cache accesses.

    Abstract translation: 一种包括本地到全局虚拟地址转换器的虚拟存储器系统，用于将具有相关联的任务特定地址空间的本地虚拟地址转换成对应于与多个任务相关联的地址空间的全局虚拟地址，以及全局虚拟到物理地址转换器， 将全局虚拟地址转换为物理地址。 保护信息由本地虚拟到全局虚拟地址转换器，全球虚拟到物理地址转换器，高速缓存标签存储器或保护信息缓冲器中的每一个提供，取决于在给定的时间段期间是否发生高速缓存命中或未命中 数据或指令访问。 高速缓存是可配置的，使得其可以被配置为缓存部分或高速缓存部分以用于更快的高速缓存访​​问。

    General purpose, dynamic partitioning, programmable media processor
    119.
    发明授权
    General purpose, dynamic partitioning, programmable media processor 有权
    通用，动态分区，可编程媒体处理器

    公开(公告)号：US6006318A

    公开(公告)日：1999-12-21

    申请号：US169963

    申请日：1998-10-13

    Applicant: Craig C. Hansen ,  John Moussouris

    Inventor： Craig C. Hansen ,  John Moussouris

    IPC: G06F9/30 ,  G06F9/308 ,  G06F9/315 ,  G06F9/38 ,  G06F12/08 ,  G06F12/10 ,  G06F15/78 ,  H04N21/426 ,  H04N21/43 ,  H04N21/433 ,  H04N21/4363 ,  H04N21/462 ,  G06F9/00

    CPC classification number: G06F9/30018 ,  G06F12/0875 ,  G06F12/1027 ,  G06F15/7832 ,  G06F15/7842 ,  G06F9/30 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/3802 ,  G06F9/3867 ,  G06F9/3869 ,  H04N21/426 ,  H04N21/4331 ,  H04N21/4363 ,  H04N21/4622 ,  G06F2212/2515 ,  H04N21/4305

    Abstract: A general purpose, programmable media processor for processing and transmitting a media data stream of audio, video, radio, graphics, encryption, authentication, and networking information in real-time. The media processor incorporates an execution unit that maintains substantially peak data throughout of media data streams. The execution unit includes a dynamically partionable multi-precision arithmetic unit, programmable switch and programmable extended mathematical element. A high bandwidth external interface supplies media data streams at substantially peak rates to a general purpose register file and the multi-precision execution unit. A memory management unit, and instruction and data cache/buffers are also provided. High bandwidth memory controllers are linked in series to provide a memory channel to the general purpose, programmable media processor. The general purpose, programmable media processor is disposed in a network fabric consisting of fiber optic cable, coaxial cable and twisted pair wires to transmit, process and receive single or unified media data streams. Parallel general purpose media processors are disposed throughout the network in a distributed virtual manner to allow for multi-processor operations and sharing of resources through the network. A method for receiving, processing and transmitting media data streams over the communications fabric is also provided.

    Abstract translation: 一种通用的可编程媒体处理器，用于实时处理和传输音频，视频，无线电，图形，加密，认证和网络信息的媒体数据流。 媒体处理器包含执行单元，其在整个媒体数据流中保持基本的峰值数据。 执行单元包括动态分立的多精度算术单元，可编程开关和可编程扩展数学元素。 高带宽外部接口以基本上峰值的速率将媒体数据流提供给通用寄存器文件和多精度执行单元。 还提供了存储器管理单元以及指令和数据高速缓冲存储器/缓冲器。 高带宽存储器控制器串联连接，为通用的可编程媒体处理器提供存储通道。 通用的可编程媒体处理器被布置在由光纤电缆，同轴电缆和双绞线组成的网络结构中，以传输，处理和接收单个或统一的媒体数据流。 平行通用媒体处理器以分布式虚拟方式在整个网络中进行布置，以允许通过网络进行多处理器操作和资源共享。 还提供了一种用于通过通信结构接收，处理和传送媒体数据流的方法。

    Technique of incorporating floating point information into processor instructions
    120.
    发明授权
    Technique of incorporating floating point information into processor instructions 失效
    将浮点信息合并到处理器指令中的技术

    公开(公告)号：US5812439A

    公开(公告)日：1998-09-22

    申请号：US541643

    申请日：1995-10-10

    Applicant: Craig C. Hansen

    Inventor： Craig C. Hansen

    IPC: G06F9/302 ,  G06F9/318 ,  G06F9/38 ,  G06F7/38

    CPC classification number: G06F9/30189 ,  G06F9/30014 ,  G06F9/3865

    Abstract: A floating point system and method employing instructions where instruction have incorporated floating point information. The floating point information indicates whether an exception trap should occur and the type of rounding to be performed upon "inexact" arithmetic results. The floating point information further indicates whether other floating-point exception traps should occur. This information allows dynamic (e.g. instruction-by-instruction) modification of various operating parameters of the CPU without modifying information in status registers using special instructions or modes, thereby increasing overall CPU performance. The technique is also supported by several mechanisms for providing precise floating-point exceptions.

    Abstract translation: 一种浮点系统和采用指令的方法，其中指令包含浮点信息。 浮点信息指示是否发生异常陷阱，并在“不精确”运算结果时执行舍入的类型。 浮点信息还指示是否应发生其他浮点异常捕获。 该信息允许在不使用特殊指令或模式修改状态寄存器中的信息的情况下对CPU的各种操作参数进行动态（例如逐个指令）修改，从而提高整体CPU性能。 该技术还通过几种提供精确浮点异常的机制来支持。

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