Abstract:
A method for mounting a LSI chip (1) with conductive bumps (2, 3, 4) as terminals into a hole (15) of a card (5) and for interconnecting them. The card and therefore one end of the hole is first covered by a layer (16) of a conductive material. Then the conductive bumps of the chip placed in the hole are soldered to the layer whilst being pressed against this layer. Thus protrusions (17, 18, 19) are created on the external surface of the layer. These protrusions are used to facilitate the alignment of the mask used during the subsequent etching operation of the layer. The invention also concerns a process for creating the conductive bumps (2, 3, 4) on the terminal pads (6, 7, 8) of the LSI chip (1).
Abstract:
Correction arrangement, for an amplifier, with two correction circuits (CS1,PM2,NM3/2,CS2,NM4,PM4/3) each connected in parallel across the output stage (PM1,NM1) of the amplifier provided with an input differential amplifier stage (A1), with two differential amplifiers (A2/3) constituting an intermediate stage and with the output stage constituted by the series connection of a PMOS transistor (PM1) and an NMOS transistor (NM1) the junction point (VOUT) of which is connected to the input stage via a feedback circuit (FC). Each correction circuit is able to measure the DC current (I1;I2) through an output transistor (PM1, NM1), to compare a measuring DC current (I3;I4) derived from this measured DC current with a reference DC current (I5;I6) and to change the DC voltage on the gate of the other output transistor (NM1;PM1) in function of the difference and to thus produce a correcting function on the amplifier through the feedback circuit.
Abstract:
A device (MAM) including a common data resource (RAM) to which a first (PR) and several second (LC) stations are coupled. This device includes a first transmission circuit (DB, MD, LD2, LD1, DBU) coupling the common resource and the first station and, for each of the second stations, a second transmission circuit (DB, MD) coupling the common resource and a buffer circuit (LR; LW) and a third transmission circuit (PISO, SO; SI, SIPO) coupling the buffer circuit and the corresponding second station and which is used at predetermined moments (T1, T2, T3; T4). The device also includes a priority circuit (CLC, SG) which grants the highest priority to the requests for the use of the first transmission circuit and the following priorities to the requests for the use of the second transmission circuits in decreasing order of the frequencies (SOS; SIS) of the corresponding predetermined moments.
Abstract:
Asynchronous time division system including at least one node with a switching network (BSN) to which a plurality of user stations (US1/N) are coupled via transmission links and which is adapted to interconnect user stations. At least one (US4) of these user stations is a clock station providing clock information, and upon the establishment of a connection between a plurality of other user stations (US1/3), with the purpose of exchanging synchronous data, each of these stations establishes a connection with this clock station.
Abstract:
Telecommunication line circuit with line amplifiers having a bias voltage equal to the sum of a fixed voltage and a variable voltage which is function of the envelope of a metering signal. A polarity reversal circuit is able to change the output voltage of each of these line amplifiers between two predetermined voltages in a gradual way and independently from the line circuit.
Abstract:
Electrically conductive device constituted by a male connector (1) comprising two end flanges (4, 5) and an electrically conductive bottom part (3) holding a plurality of a male contacts which are adapted to cooperate with the female contacts (12) of a female connector (8). When these connectors are interconnected the female contacts are electrically interconnected and a gap (14) between the connectors (1, 8) permits cleaning of these contacts.
Abstract:
Electronic contacts and associated devices include a voltage protection device (D1 to D5, Q4, 05, Q7) and a current protection device (R2, Q4, Q6, Q7) for placing an electronic contact (TRX) in the open state when the voltage across and the current flowing in the latter exceed a predetermined voltage (VD) and current (11) values respectively. The predetermined voltage value (VD) is slightly larger than the one (V1) which corresponds to the predetermined current value (11) in the current versus voltage characteristic of this electronic contact.
Abstract:
The invention relates to switching circuits and matrix device using same and having the form of a flat panel comprising a control device and a smectic liquid crystal display including pixels arranged in a coordinate matrix of 400 rows and 720 columns. The control device includes several driver units located along the four sides of the rectangular matrix and serially interconnected along each side so as to constitute bidirectional shift registers for serial control data and information. Each driver unit controls 30 odd or 30 even numbered lines (rows or columns) and is able to apply to these lines for a predetermined duration DC voltages equal to either -150 Volts, -30 Volts, 0 Volt, +30 Volts or +150 Volts in function of these data and information.
Abstract:
A telecommunication switching system including a plurality of terminal circuits with a common control device coupled with a switching network through a plurality of interface circuits (TCEA/B) operating asynchronously. The common control device includes a processor (PROM, LU, PCA/B, MUX3) and control means (AUTOMATON) to successively allocate that processor to one of the interface circuits.