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    Fuzzy multi-stage inference processor
    111.
    发明公开
    Fuzzy multi-stage inference processor 失效
    模糊多级推理处理器

    公开(公告)号：EP0798631A1

    公开(公告)日：1997-10-01

    申请号：EP96830173.9

    申请日：1996-03-29

    Applicant: CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO

    Inventor： Cuce, Antonino

    IPC: G06F7/00

    CPC classification number: G06N7/04

    Abstract: This invention relates to a fuzzy processor having an input X for at least a plurality of input variables X-i and an output U for one or more output results U-k, and comprising a fuzzyfication unit FU having an input coupled to the input X, a fuzzy rule processing unit RU having an input coupled to the output of the fuzzyfication unit FU, and a defuzzyfication unit DU having an input coupled to the output of the processing unit CU and an output coupled to said output U, wherein the output of the defuzzyfication unit DU is coupled to the input of the fuzzyfication unit FU and/or to the input of the processing unit RU.

    Abstract translation: 本发明涉及一种模糊处理器，其具有用于至少多个输入变量Xi的输入X和用于一个或多个输出结果Uk的输出U，并且包括具有耦合到输入X的输入的模糊化单元FU，模糊规则 具有耦合到模糊化单元FU的输出的输入的处理单元RU和具有耦合到处理单元CU的输出的输入和耦合到所述输出U的输出的解消化单元DU，其中解消化单元DU的输出 耦合到模糊化单元FU的输入端和/或耦合到处理单元RU的输入端。

    Current limitation programmable circuit for smart power actuators
    112.
    发明公开
    Current limitation programmable circuit for smart power actuators 失效
    Programmierbare Schaltung mit StrombegrenzungfürLeistungsstellantriebe

    公开(公告)号：EP0793343A1

    公开(公告)日：1997-09-03

    申请号：EP96830089.7

    申请日：1996-02-29

    Applicant: CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO

    Inventor： Pulvirenti, Francesco

    IPC: H03K17/082

    CPC classification number: H03K17/0822

    Abstract: A circuit for limitation of maximum current delivered by a power transistor (PW) comprises:

    A network for detection of the current delivered by the power transistor (PW) which generates a first electrical signal,
    a reference network for generating a reference current (IR) proportional to a resistor (Rext) and self-limited, provided by means of a current generator circuit (5) and a limiting circuit (6) with current mirror, and

    an operational amplifier (3) which compares the first electrical signal with the reference current (IR) and which tends to inhibit the power transistor (PW) if the current delivered exceeds a certain threshold value.

    Abstract translation: 用于限制由功率晶体管（PW）传送的最大电流的电路包括：用于检测由功率晶体管（PW）传递的产生第一电信号的电流的网络，用于产生参考电流（IR）的参考网络， 与由电流发生器电路（5）和具有电流镜的限制电路（6）提供的电阻（Rext）和自限制成比例;以及运算放大器（3），其将第一电信号与参考电压 电流（IR），并且如果输出的电流超过某一阈值，则趋向于抑制功率晶体管（PW）。

    Driving circuit, MOS transistor using the same and corresponding applications
    116.
    发明公开
    Driving circuit, MOS transistor using the same and corresponding applications 失效
    Steuerungsschaltung，MOS晶体管mit solch einer Schaltung

    公开(公告)号：EP0757512A1

    公开(公告)日：1997-02-05

    申请号：EP95830341.4

    申请日：1995-07-31

    Applicant: SGS-THOMSON MICROELECTRONICS S.r.l. ,  CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO

    Inventor： Palara, Sergio ,  Graziano, Vito

    IPC: H05B41/00 ,  H03K17/687 ,  H02M7/5383 ,  H05B41/29

    CPC classification number: H03K17/04123 ,  H03K17/302 ,  H05B41/2825

    Abstract: A first principle on which the driver circuit of this invention operates is to delay the turning on of the MOS transistor (M2) by utilizing the time-wise pattern of the circuit input (G) signal rather than generating a delay within the circuit itself. The basic idea is one of using a threshold type of circuit element and arranging for no current to flow toward or from, depending on the type of the MOS transistor, the control terminal before the voltage at the circuit input exceeds a predetermined value. This is achieved, for example, by coupling a Zener diode (D1) serially to the control terminal. Where the input signal is of a kind which increases with a degree of uniformity, the time required to exceed that threshold will correspond to the desired delay. Thus, the driver circuit can match the dynamic range of the input signal automatically.

    Abstract translation: 本发明的驱动电路工作的第一原理是通过利用电路输入（G）信号的时间图案来延迟MOS晶体管（M2）的导通，而不是在电路本身内产生延迟。 基本思想是使用阈值类型的电路元件，并且根据MOS晶体管的类型，在电路输入端的电压之前的控制端子超过预定值时，不会流向或不流过电流。 这通过例如将齐纳二极管（D1）串联耦合到控制端来实现。 在输入信号是以均匀度增加的类型的情况下，超过该阈值所需的时间将对应于期望的延迟。 因此，驱动电路可以自动匹配输入信号的动态范围。

    Improved IGBT device
    118.
    发明公开
    Improved IGBT device 失效
    Verbesserte IGBT-Anordnung

    公开(公告)号：EP0746040A1

    公开(公告)日：1996-12-04

    申请号：EP95830228.3

    申请日：1995-05-31

    Applicant: CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO

    Inventor： Fragapane, Leonardo ,  Frisina, Ferruccio

    IPC: H01L29/739

    CPC classification number: H01L29/7395

    Abstract: A semiconductor power device comprising an isolated gate bipolar transistor, of the type which comprises a semiconductor substrate with a first type of conductivity and an overlying epitaxial layer with a second type of conductivity, opposite from the first, and whose junction to the substrate forms the base/emitter junction of the bipolar transistor, has the junction formed by a layer of semiconductor material with conductivity of the second type but a higher concentration of dopant than that of the epitaxial layer.
    Furthermore, the device has the epitaxial layer with conductivity of the second type provided with at least two zones at different dopant concentrations, namely a first lower zone being part of the junction and having a higher dopant concentration, and a second upper zone having a lower concentration.

    Abstract translation: 一种半导体功率器件，包括隔离栅极双极晶体管，其类型包括具有第一类型导电性的半导体衬底和具有与第一类型相反的第二导电类型的上覆外延层，并且其与衬底的结到形成 双极晶体管的基极/发射极结具有由具有第二类型的导电性但具有比外延层更高的掺杂剂浓度的半导体材料层形成的结。 此外，该器件具有第二类型的具有导电性的外延层，其具有不同掺杂浓度的至少两个区域，即作为结的一部分并具有较高掺杂剂浓度的第一下部区域，以及具有较低掺杂剂浓度的第二上部区域 浓度。

    Circuit for generating a reference voltage and detecting an undervoltage of a supply voltage and corresponding method
    119.
    发明公开
    Circuit for generating a reference voltage and detecting an undervoltage of a supply voltage and corresponding method 失效
    用于产生参考电压，并检测电源电压的下降和相关联的方法的电路装置

    公开(公告)号：EP0733959A1

    公开(公告)日：1996-09-25

    申请号：EP95830111.1

    申请日：1995-03-24

    Applicant: CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO ,  SGS-THOMSON MICROELECTRONICS S.r.l.

    Inventor： Gariboldi, Roberto ,  Pulvirenti, Francesco

    IPC: G05F3/26 ,  G05F3/28

    CPC classification number: G11C5/147 ,  G05F1/465 ,  G05F3/267

    Abstract: A circuit for generating a reference voltage and detecting a drop in a supply voltage, comprising at least one threshold comparator (12) having an input terminal (IN) and an output terminal, and a voltage divider (14) connected between a first supply voltage reference (Vs) and a second voltage reference (GND) and connected to the input terminal (IN) of the comparator (12), further provides for the output terminal (OUT) of said comparator (12) to be connected to the input terminal (IN) through at least one feedback network comprising at least one current generator (CG1).
    The feedback network further comprises a buffer block (13) having an input terminal connected to said comparator (12) and a first output terminal (DO) connected to a switch (SW) which is connected between a circuit node (X2) of said voltage divider (14) and the second voltage reference (GND).

    Abstract translation: 连接在第一电源电压之间，用于产生参考电压，并检测在供电电压下降的电路，包括：具有输入端（IN）上，并输出终端的至少一个阈值比较器（12），和一个电压分压器（14） 参考（VS）和一个第二电压基准（GND）和连接到所述比较器（12）的输入端（IN），还提供了用于所述比较器（12）的输出端（OUT）被连接到输入端 （IN）通过至少一个反馈网络，其包括至少一个电流发生器（CG1）。 反馈网络还包括具有连接到连接到被连接在所述电压的电路节点（X2）之间的开关（SW）所有的所述比较器（12）和第一输出端（DO）输入端一个缓冲器块（13） 除法器（14）和所述第二电压基准（GND）。

    A semiconductor particle-detector and methods for the manufacture thereof
    120.
    发明公开
    A semiconductor particle-detector and methods for the manufacture thereof 失效
    Halbleiterteilchendetektor und Verfahren zu seiner Herstellung

    公开(公告)号：EP0730304A1

    公开(公告)日：1996-09-04

    申请号：EP95830060.0

    申请日：1995-02-27

    Applicant: CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO

    Inventor： Fallica, Piero Giorgio

    IPC: H01L29/00 ,  H01L31/115 ,  H01L31/118

    CPC classification number: H01L31/118 ,  H01L31/115

    Abstract: A particle-detector is formed on a die of semiconductor material (20) comprising: first and second layers (22, 23) with a first type of conductivity (N), a third layer (21) with a second type of conductivity (P), interposed between the first and second layers (22, 23), first and second means (25, 31; 26, 32) for electrical connection with the first and second layers (22, 23), respectively, disposed on the opposite surfaces thereof to those of the junctions with the third layer (21) and third means (27, 24) for electrical connection with the third layer (21).
    To permit large-scale industrial manufacture, the third means (27, 24) for electrical connection with the third layer (21) comprise a region (24) with the second type of conductivity (P) which extends from the front face of the die as far as the third layer (21) and means (27) for surface electrical contact with this region.

    Abstract translation: 粒子检测器形成在半导体材料（20）的管芯上，包括：具有第一导电类型（N）的第一和第二层（22,23），具有第二导电类型的第三层（21） ）插入在第一和第二层（22,23）之间，分别与设置在相对表面上的第一和第二层（22,23）电连接的第一和第二装置（25,31; 26,32） 与第三层（21）的接合部和与第三层（21）电连接的第三装置（27,24）。 为了允许大规模工业制造，用于与第三层（21）电连接的第三装置（27,24）包括具有第二导电类型（P）的区域（24），该区域从模具的前表面延伸 直到第三层（21）和用于与该区域表面电接触的装置（27）。

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