公开(公告)号：US20030005402A1

公开(公告)日：2003-01-02

申请号：US10186314

申请日：2002-06-28

Applicant: STMicroelectronics Ltd.

Inventor： Ankur Bal

IPC: G06F017/50

CPC classification number: H03K19/1776 ,  H03K19/17736 ,  H03K19/17744

Abstract: A system for simplifying the programmable memory-to-logic interface in field programmable gate arrays (FPGAs) is provided. An interface may be used to isolate the general purpose routing architecture for intra-programmable logic blocks (PLBs) from the random access memory (RAM) address lines, data lines, and control lines. The PLBs and the input-output resources of the FPGA access the embedded memory (or RAM) using dedicated direct interconnects. Certain of these direct interconnects may originate from PLBs in the vicinity of the RAM. The remainder run between the input-output (IO) pads/routing and the RAM blocks. A bus routing architecture is also provided to combine the memories to emulate larger RAM blocks. This bus routing provides interconnection among RAM blocks and is isolated from the PLB routing resources.

Abstract translation: 提供了一种用于简化现场可编程门阵列（FPGA）中的可编程存储器到逻辑接口的系统。 可以使用接口来隔离来自随机存取存储器（RAM）地址线，数据线和控制线的可编程逻辑块（PLB）的通用路由架构。 FPGA的PLB和输入输出资源使用专用直接互连访问嵌入式存储器（或RAM）。 这些直接互连中的某些可能来自RAM附近的PLB。 剩余部分在输入 - 输出（IO）焊盘/路由和RAM块之间运行。 还提供总线路由架构以组合存储器以模拟较大的RAM块。 该总线路由提供RAM块之间的互连，并与PLB路由资源隔离。

公开(公告)号：US20020114200A1

公开(公告)日：2002-08-22

申请号：US10072458

申请日：2002-02-07

Applicant: STMicroelectronics Ltd.

Inventor： Ankur Bal

IPC: G11C007/00

CPC classification number: H03K19/17776

Abstract: A system for relatively rapidly configuring reconfigurable devices with a plurality of latches is provided. The number of clock cycles for loading the configuration data may be reduced by a substantial amount, and the fidelity of data loaded into the configuration latches may be relatively high. The invention also incorporates procedures for configuring multiple reconfigurable devices, which are similar to daisy chaining techniques.

Abstract translation: 提供了一种用于相对快速地配置具有多个锁存器的可重新配置设备的系统。 用于加载配置数据的时钟周期的数量可以减少大量，并且加载到配置锁存器中的数据的保真度可能相对较高。 本发明还包括用于配置多个可重新配置设备的过程，其类似于菊花链技术。

公开(公告)号：US20020114025A1

公开(公告)日：2002-08-22

申请号：US09993387

申请日：2001-11-16

Applicant: STMicroelectronics Ltd

Inventor： Jeffrey Raynor ,  Peter Denyer ,  Jonathan Ephriam David Hurwitz

IPC: H04N001/46

CPC classification number: H04N5/37452 ,  H04N5/353 ,  H04N5/3575 ,  H04N5/378

Abstract: An image plane includes a plurality of pixels. Each pixel comprises a photodiode and two transistors, and each pixel is connected by a signal bus to a respective storage node located off the image plane. Each storage node comprises two capacitors and associated switches. One of the transistors applies a reset pulse to the pixel, and the other transistor connects the pixel to a given conductor of the signal bus, which is then connected to the storage node. The pixel transistors can be operated simultaneously, and the sensed values can subsequently be transferred from the storage nodes sequentially.

Abstract translation: 图像平面包括多个像素。 每个像素包括光电二极管和两个晶体管，并且每个像素通过信号总线连接到位于图像平面外的相应存储节点。 每个存储节点包括两个电容器和相关联的开关。 其中一个晶体管将复位脉冲施加到像素，另一个晶体管将像素连接到信号总线的给定导体，该导体然后连接到存储节点。 像素晶体管可以同时操作，并且随后可以从存储节点依次传送感测值。

公开(公告)号：US20020113618A1

公开(公告)日：2002-08-22

申请号：US10072461

申请日：2002-02-07

Applicant: STMicroelectronics Ltd.

Inventor： Ankur Bal

IPC: H03K019/173

CPC classification number: H03K19/17748 ,  H03K19/17728 ,  H03K19/17736

Abstract: A programmable logic device may include a programmable interconnect structure and a plurality of configurable logic elements including data latches interconnected by the interconnect structure. At least one of the configurable logic elements may be configurable as both a shift register and a lookup table. Also, the shift register may be enabled to operate as a bi-directional shift register by the inclusion of a first circuit for configuring the data latches either as series-connected inverters during a shift operation or as data latches after each shift operation. A second circuit for selecting a direction of shifting may also be included, as well as a third circuit for supplying data to the input of the shift register as determined by the direction of shifting.

Abstract translation: 可编程逻辑器件可以包括可编程互连结构以及包括通过互连结构互连的数据锁存器的多个可配置逻辑元件。 可配置逻辑元件中的至少一个可以被配置为移位寄存器和查找表。 此外，移位寄存器可以通过在移位操作期间包括用于配置数据锁存器作为串联连接的反相器的第一电路或者在每个移位操作之后的数据锁存器中而被允许作为双向移位寄存器操作。 还可以包括用于选择移位方向的第二电路，以及用于向由移位方向确定的移位寄存器的输入端提供数据的第三电路。

公开(公告)号：US20020079943A1

公开(公告)日：2002-06-27

申请号：US09988883

申请日：2001-11-20

Applicant: STMicroelectronics Ltd.

Inventor： Prashant Dubey

IPC: G06F001/04

CPC classification number: H03K3/0315 ,  G06F1/04 ,  G06F1/08 ,  H03K3/017

Abstract: A digital clock generator circuit with built-in frequency and duty cycle control may include a pulse generator for generating a start pulse. The pulse generator may be connected to a ring oscillator to generate multiple signals having a specified frequency and programmable duty cycles. The oscillator may further be connected to a multiplexer which selectively connects one output of the ring oscillator to a final output to produce a signal of the specified frequency and specified duty cycle. The duty cycle may be adjustable over a wide range and across the full frequency band of operation.

Abstract translation: 具有内置频率和占空比控制的数字时钟发生器电路可以包括用于产生起始脉冲的脉冲发生器。 脉冲发生器可以连接到环形振荡器以产生具有指定频率和可编程占空比的多个信号。 振荡器还可以连接到选择性地将环形振荡器的一个输出连接到最终输出以产生指定频率和指定占空比的信号的多路复用器。 占空比可以在宽范围和整个工作频带范围内调节。

公开(公告)号：US12148778B2

公开(公告)日：2024-11-19

申请号：US17243195

申请日：2021-04-28

Applicant: STMICROELECTRONICS LTD.

Inventor： Yu-Tsung Lin

IPC: H01L27/146 ,  G02B3/00 ,  G03F7/00

Abstract: A method of forming a device, the method including: depositing a first photoresist layer over a substrate, forming an array of seed lenses by patterning and reflowing the first photoresist layer, a dimension of the array of seed lenses varying across the substrate, forming a second photoresist layer over the array of seed lenses, and forming a microlens array by patterning and reflowing the second photoresist layer.

公开(公告)号：US12001012B2

公开(公告)日：2024-06-04

申请号：US17238596

申请日：2021-04-23

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics Ltd

Inventor： Davide Terzi ,  Gianluca Mendicino ,  Dadi Sharon

IPC: G02B26/10 ,  B81B3/00 ,  G02B26/08 ,  G09G3/34 ,  H02N2/10 ,  H02N2/14 ,  H03H9/15 ,  H10N30/20 ,  H10N30/853

CPC classification number: G02B26/101 ,  B81B3/0021 ,  G02B26/0858 ,  G09G3/346 ,  H02N2/103 ,  H02N2/145 ,  H03H9/15 ,  H10N30/204 ,  B81B2201/032 ,  H10N30/8554

Abstract: Disclosed herein is a microelectromechanical (MEMS) device, including a rotor and a first piezoelectric actuator mechanically coupled to the rotor. The first piezoelectric actuator is electrically coupled between a first signal node and a common voltage node. A second piezoelectric actuator is mechanically coupled to the rotor, and is electrically coupled between a second signal node and the common voltage node. Control circuitry includes a drive circuit configured to drive the first and second piezoelectric actuators, a sense circuit configured to process sense signals generated by the first and second pizeoelectric actuators, and a multiplexing circuit. The multiplexing circuit is configured to alternate between connecting the drive circuit to the first piezoelectric actuator while connecting the sense circuit to the second piezoelectric actuator, and connecting the drive circuit to the second piezoelectric actuator while connecting the sense circuit to the first piezoelectric actuator.

公开(公告)号：US11887958B2

公开(公告)日：2024-01-30

申请号：US17403752

申请日：2021-08-16

Applicant: STMICROELECTRONICS LTD

Inventor： Cheng-Yang Su

IPC: H01L23/00

CPC classification number: H01L24/14 ,  H01L24/11 ,  H01L2224/11462 ,  H01L2224/1403 ,  H01L2224/1405

Abstract: A die including a first contact with a first shape (e.g., ring-shaped) and a second contact with a second shape (e.g., cylindrical shaped) different from the first shape. The first contact has an opening that extends through a central region of a surface of the first contact. A first solder portion is coupled to the surface of the first contact and the first solder portion has the first shape. A second solder portion is coupled to a surface of the second contact and the second solder portion has the second shape. The first solder portion and the second solder portion both have respective points furthest away from a substrate of the die. These respective points of the first solder portion and the second solder portion are co-planar with each other such that a standoff height of the die remains consistent when coupled to a PCB or an electronic component.

公开(公告)号：US11742437B2

公开(公告)日：2023-08-29

申请号：US17187510

申请日：2021-02-26

Applicant: STMICROELECTRONICS LTD ,  STMICROELECTRONICS PTE LTD

Inventor： David Gani ,  Yiying Kuo

IPC: H01L31/0203 ,  H01L31/18 ,  H01L31/0392 ,  H01L31/02 ,  H01L21/78

CPC classification number: H01L31/0203 ,  H01L21/78 ,  H01L31/02002 ,  H01L31/02005 ,  H01L31/0392 ,  H01L31/1876 ,  H01L31/1896

Abstract: The present disclosure is directed to a package, such as a wafer level chip scale package (WLCSP), with a die coupled to a central portion of a transparent substrate. The transparent substrate includes a central portion having and a peripheral portion surrounding the central portion. The package includes a conductive layer coupled to a contact of the die within the package that extends from the transparent substrate to an active surface of the package. The active surface is utilized to mount the package within an electronic device or to a printed circuit board (PCB) accordingly. The package includes a first insulating layer separating the die from the conductive layer, and a second insulating layer on the conductive layer.

公开(公告)号：US20230090636A1

公开(公告)日：2023-03-23

申请号：US17479345

申请日：2021-09-20

Applicant: STMicroelectronics LTD ,  STMicroelectronics S.r.l.

Inventor： Alex DOMNITS ,  Elan ROTH ,  Davide TERZI ,  Luca MOLINARI ,  Marco BOSCHI

IPC: G03B21/14 ,  G03B21/00 ,  G03B21/20 ,  G01J1/02 ,  G01J1/44

Abstract: A scanning laser projector includes an optical module and projection engine. The optical module includes a laser generator outputting a laser beam, and a movable mirror scanning the laser beam across an exit window defined through the housing in a scanning pattern wider than the exit window such that the laser beam is directed through the exit window in a projection pattern that is smaller than and within the scanning pattern. A first light detector is positioned about a periphery of the exit window such that as the movable mirror scans the laser beam in the scan pattern, at a point in the scan pattern where the laser beam is scanned across an interior of the housing and not through the exit window, the laser beam impinges upon the first light detector. The projection engine adjusts driving of the movable mirror based upon output from the first light detector.