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公开(公告)号：KR1019950007438B1
公开(公告)日：1995-07-10
申请号：KR1019910026081
申请日：1991-12-30
IPC: H04L12/403 , H04L12/40
Abstract: When transmitting packet, the arbitrator arbitrates packet data transfer not to cause conflict and efficiently uses information by using each equipment equally. To improve processing capability of the packet call control processor and enlarge link capacity per packet processing sub-system, this central arbitrator employs eight packet call control processors and twenty packets processing arbitrators. This system consists of a packet call control processor(11), packet call control processor arbitrators(12, 13), central arbitrators(14, 15), packet processing arbitrators(16, 17) and a packet processor(18).
Abstract translation: 仲裁员在发送数据包时，会对数据包传输进行仲裁，而不会引起冲突，并通过平均使用每个设备有效地使用信息。 为了提高分组呼叫控制处理器的处理能力并扩大每个分组处理子系统的链路容量，该中心仲裁器采用8个分组呼叫控制处理器和20个分组处理仲裁器。 该系统包括分组呼叫控制处理器（11），分组呼叫控制处理器仲裁器（12,13），中央仲裁器（14,15），分组处理仲裁器（16,17）和分组处理器（18）。
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公开(公告)号：KR1019950005641B1
公开(公告)日：1995-05-27
申请号：KR1019920004382
申请日：1992-03-17
Abstract: The packet call controlling processor arbitrator is implemented in alarge number of packet call controlling processors. When growing the processing capability of controlling processor, this arbitrator grows the capability of software and preservability of packet call. The arbitrator consists of a packet call controlling processor(11), dualized packet call controlling processor arbitrators(12, 13), direct central arbitrators(14, 15), dualized packet processing apparatuses(16, 17), a packet processing block(18) and a packet bus arbitrator(19).
Abstract translation: 分组呼叫控制处理器仲裁器在大量数据包呼叫控制处理器中实现。 当增加控制处理器的处理能力时，该仲裁员增加了数据包呼叫的软件和可维护性的能力。 仲裁器由分组呼叫控制处理器（11），二元化分组呼叫控制处理器仲裁器（12,13），直接中央仲裁器（14,15），二元化分组处理设备（16,17），分组处理模块（18） ）和分组总线仲裁器（19）。
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公开(公告)号：KR1019950005148B1
公开(公告)日：1995-05-18
申请号：KR1019910023139
申请日：1991-12-17
IPC: H04L12/40
Abstract: When data transmission between packet processing units or between a control processor and packet processing unit, the selection circuit selects multiple packet bus which enhances reliability of data transmission. Selection circuit comprises interrupt processing unit to generate operate/wait selection control interrupt to packet processing unit; state change detection unit to generating operate/wait state change interrupt by comparing old state and current state of operate/wait signal.
Abstract translation: 当分组处理单元之间或控制处理器与分组处理单元之间的数据传输时，选择电路选择多个分组总线，增强数据传输的可靠性。 选择电路包括中断处理单元，对分组处理单元产生操作/等待选择控制中断; 状态变化检测单元通过比较操作/等待信号的旧状态和当前状态来产生操作/等待状态改变中断。
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公开(公告)号：KR1019950001517B1
公开(公告)日：1995-02-25
申请号：KR1019910023138
申请日：1991-12-17
IPC: H04L12/40
Abstract: The control circuit eliminates copy function of memory sharing method in the packet switching block of switch. This circuit increases the reliability of packet switching and controls packet efficiently and economically by centralizing control function. The circuit consists of a packet call control processor (1), dualized packet buses (2,3), a packet bus block (7), packet processors (4,5) and a packet processor block (8). Packet bus interface block (8) consists of a CPU (15), a packet common memory (16), a VME bus interface (17), a dualized packet bus controller (12), a control bus interface (13), a data bus interface (14).
Abstract translation: 控制电路消除了交换机的分组交换块中的存储器共享方法的复制功能。 该电路通过集中控制功能，提高了分组交换的可靠性，有效且经济地控制了数据包。 电路由分组呼叫控制处理器（1），二元化分组总线（2,3），分组总线模块（7），分组处理器（4,5）和分组处理器模块（8）组成。 分组总线接口块（8）由CPU（15），分组公共存储器（16），VME总线接口（17），二元化分组总线控制器（12），控制总线接口（13），数据 总线接口（14）。
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Patent Agency Ranking
公开(公告)号：KR1019940010847B1
公开(公告)日：1994-11-17
申请号：KR1019910006885
申请日：1991-04-29
IPC: H04L12/40 , H04L12/801
Abstract: The bus occupation arbitrator controls the situation when processors occupy packet bus to send or receive the data. This arbitrator enhances quality of service providing many bus occupation opportunities to the packet controller. Packet subscribers are connected to the packet switching system through a time switch (6) and the packet switching system is connected to an inter-process communication bus (5). This arbitrator provides services through X.25 protocol controlled by high-level processor (4) connected to the inter-process communication bus. A packet switching system is composed of the bus occupation arbitrator (1), a packet call controller (2) and a packet processor (3).
Abstract translation: 总线占用仲裁员控制处理器占用分组总线发送或接收数据时的情况。 该仲裁员提高了服务质量，为数据包控制器提供许多总线占用机会。 分组用户通过时间交换机（6）连接到分组交换系统，并且分组交换系统连接到进程间通信总线（5）。 该仲裁器通过连接到进程间通信总线的高级别处理器（4）控制的X.25协议提供服务。 分组交换系统由总线占用仲裁器（1），分组呼叫控制器（2）和分组处理器（3）组成。
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公开(公告)号：KR1019930015469A
公开(公告)日：1993-07-24
申请号：KR1019910026073
申请日：1991-12-30
IPC: H04L12/801 , H04L29/06 , H04L12/26
Abstract: 본 발명은 전자 교환기내에서 패킷 서비스를 수행하는 패킷교환장치에 관한 것으로, 패킷 교환은 대화형 컴퓨터 트래픽에서 폭주하는 데이터를 적절히 취급할수 있는 네트워크를 구축하는 한가지 방법으로서, 패킷은 '소포′를 의미한다. 즉, 데이터 통신을 수행할때 데이터를 일정깊이로 분할하여 각각에 수신축 주소와 제어 정보를 부가하여 하나의 작은 소포 단위로 구성한 것인데, 패킷 교환은 이 패킷 단위로 정보의 전송 및 교환을 수행하는 방식이다.
따라서, 본 발명의 목적은 장치의 연결 및 확정이 용이하고 패킷처리 효율을 향상시킬수 있는 패킷 교환장치를 제공하기 위한 것이다. -
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