公开(公告)号：KR100833515B1

公开(公告)日：2008-05-29

申请号：KR1020070021965

申请日：2007-03-06

Applicant: 한국전자통신연구원

Inventor： 오종의 ,  윤찬호 ,  정민호 ,  이유로 ,  이석규 ,  유희정 ,  방승찬

IPC: H03M13/11

CPC classification number: H03M13/116 ,  H03M13/1188 ,  H03M13/618 ,  H03M13/6356 ,  H03M13/6393

Abstract: A method for generating a parity check matrix of an LDPC code having a variable information length and a variable code rate, an encoding/decoding method, and an apparatus using the same are provided to form easily a decoder of a variable information length and variable code rate by using only one parallel processing type hardware. A first parity check matrix generation process is performed to generate a first parity check matrix including a first information block and a parity block. An mth parity check matrix generation process is performed to generate an mth parity check matrix by adding an mth information block to a generated m-1th parity check matrix. The mth parity check matrix generation process includes a process for generating the mth parity check matrix by optimizing degree distribution and cycle distribution.

Abstract translation: 提供一种用于生成具有可变信息长度和可变码率的LDPC码的奇偶校验矩阵的方法，编码/解码方法以及使用其的装置，以便容易地形成可变信息长度和可变码的解码器 仅使用一个并行处理类型硬件的速率。 执行第一奇偶校验矩阵生成处理以生成包括第一信息块和奇偶校验块的第一奇偶校验矩阵。 执行第m个奇偶校验矩阵生成处理，以通过将第m个信息块与生成的第m-1个奇偶校验矩阵相加来生成第m个奇偶校验矩阵。 第m个奇偶校验矩阵生成处理包括通过优化度分布和周期分布来生成第m个奇偶校验矩阵的处理。

公开(公告)号：KR1020080030329A

公开(公告)日：2008-04-04

申请号：KR1020060096274

申请日：2006-09-29

Applicant: 한국전자통신연구원

Inventor： 윤찬호 ,  오종의 ,  정민호 ,  이유로 ,  이석규 ,  유희정 ,  방승찬

IPC: H03M13/11

CPC classification number: H03M13/116 ,  H03M13/1185 ,  H03M13/1188

Abstract: A method for encoding an LDPC(Low Density Parity Check) code by using a result of checking a predetermined parity is provided to effectively encode the LDPC code by slightly changing only a structure of an H matrix. A method for encoding an LDPC code by using a result of checking a predetermined parity includes the steps of: forming a parity bit check matrix with a dual diagonal structure based on an H matrix(901); calculating all parity bit by inserting an arbitrary binary number into a sub block unit(902); checking a parity bit corresponding to the sub block unit on the last position of the H matrix when the calculated parity bit is not right(903,904); searching a parity bit part where a result of checking the parity bit is represented as 1(905); performing an XOR operation of the parity bit part into which the arbitrary binary number is inserted and the parity bit part obtained through a simultaneous equation between the parity bits per the sub block unit(906); and determining, the parity bit satisfying a condition that a result of multiplying the H matrix by a code word vector encoded by the H matrix corresponds to 0, as the parity bit of the H matrix(907).

Abstract translation: 提供了通过使用检查预定奇偶校验的结果对LDPC（低密度奇偶校验）码进行编码的方法，以通过稍微改变H矩阵的结构来有效地对LDPC码进行编码。 通过使用检查预定奇偶校验的结果对LDPC码进行编码的方法包括以下步骤：基于H矩阵形成具有双对角线结构的奇偶校验位校验矩阵（901）; 通过将任意二进制数插入子块单元（902）来计算所有奇偶校验位; 当所计算的奇偶校验位不正确时，检查与H矩阵的最后位置相对应的子块单元的奇偶校验位（903,904）; 搜索奇偶校验位部分，其中检查奇偶校验位的结果被表示为1（905）; 执行插入任意二进制数的奇偶校验位部分的异或运算和通过每个子块单元（906）的奇偶校验位之间的联立方程获得的奇偶校验位部分; 并且确定满足由H矩阵编码的码字向量将H矩阵乘以H的矩阵对应于0的条件的奇偶校验位作为H矩阵的奇偶校验位（907）。

公开(公告)号：KR1020070061740A

公开(公告)日：2007-06-14

申请号：KR1020060048015

申请日：2006-05-29

Applicant: 한국전자통신연구원

Inventor： 최은영 ,  유희정 ,  윤찬호 ,  손정보 ,  이일구 ,  류득수 ,  전태현 ,  민승욱 ,  이석규

IPC: H04L27/26 ,  H04L12/28

Abstract: An apparatus and a method for controlling a receiving terminal in a next generation wireless communication system are provided to perform control according to an abnormal data processing error by monitoring an operation of each block of a wireless LAN receiving terminal. An apparatus for controlling a receiving terminal in a next generation wireless communication system includes a receiving terminal monitor module(120), a count module(130), and a control module(110). The receiving terminal monitor module(120) receives a plurality of event signals which are generated in a data signal processing process generated in the receiving terminal. The count module(130) has a counter, and operates the counter for a predetermined time corresponding to the plurality of event signals by activating or inactivating the counter. The control module(110) controls the count module(130), and controls the receiving terminal by determining whether the corresponding event signal is received for a predetermined time.

Abstract translation: 提供了一种用于控制下一代无线通信系统中的接收终端的装置和方法，用于通过监视无线LAN接收终端的每个块的操作，根据异常数据处理错误来执行控制。 一种用于在下一代无线通信系统中控制接收终端的装置，包括接收终端监视模块（120），计数模块（130）和控制模块（110）。 接收终端监视模块（120）接收在接收终端中产生的数据信号处理过程中产生的多个事件信号。 计数模块（130）具有计数器，并且通过激活或禁用计数器来操作对应于多个事件信号的预定时间的计数器。 控制模块（110）控制计数模块（130），并且通过确定在预定时间内是否接收到对应的事件信号来控制接收终端。

公开(公告)号：KR1020070061733A

公开(公告)日：2007-06-14

申请号：KR1020060032587

申请日：2006-04-11

Applicant: 한국전자통신연구원

Inventor： 손정보 ,  유희정 ,  최은영 ,  윤찬호 ,  이일구 ,  류득수 ,  전태현 ,  민승욱 ,  유광현 ,  노경주 ,  김윤주 ,  송경희 ,  이석규 ,  방승찬 ,  황승구

IPC: G06F9/445 ,  G06F9/06

Abstract: A method for designing a digital system with a high-level programming language is provided to reduce time required for simulating a program made in a low-level programming language and reduce the time required for forming a system hardware configuration with a lower program by forming the system hardware environment with the high-level programming language. An algorithm and the first variable for the desired digital system are set by using the high-level programming language. The environment similar to the desired system hardware is formed based on the set algorithm and first variable by using the high-level programming language(S110). The system environment formed in the high-level programming language is converted into the low-level programming language and is implemented to the hardware(S140).

Abstract translation: 提供了一种用于设计具有高级编程语言的数字系统的方法，以减少模拟以低级编程语言制作的程序所需的时间，并且通过形成低级编程语言来减少形成具有较低程序的系统硬件配置所需的时间 系统硬件环境采用高级编程语言。 使用高级编程语言设置算法和所需数字系统的第一个变量。 通过使用高级编程语言，基于集合算法和第一变量形成类似于期望的系统硬件的环境（S110）。 将高级编程语言形成的系统环境转换为低级编程语言，并实现到硬件（S140）。

公开(公告)号：KR100690438B1

公开(公告)日：2007-03-12

申请号：KR1020060049865

申请日：2006-06-02

Applicant: 한국전자통신연구원

Inventor： 이일구 ,  이석규 ,  유희정 ,  최은영 ,  윤찬호 ,  손정보 ,  류득수 ,  민승욱 ,  전태현 ,  방승찬 ,  황승구

IPC: H04B7/005

Abstract: An AGC(Automatic Gain Control) method having variable gain control intervals and a device thereof are provided to perform a rough gain control loop in a wireless communication system having multiple antennas, and additionally conduct a detailed gain control loop for receiving signals passing through a gain control process, thereby obtaining stable gains. RF(Radio Frequency) receivers(110) receive a plurality of the first signals through plural antennas, and perform gain control for the received first signals to output the first signals as a plurality of the second signals. A signal saturation sensor(400) outputs a saturated state determination value if the number of the second signals larger than a threshold value is more than a predetermined number. A gain controller(300) detects one power by comparing power of the second signals, and outputs the detected power and a gain determination value determined on the basis of the saturated state determination value to the RF receivers(110).

Abstract translation: 提供具有可变增益控制间隔的AGC（自动增益控制）方法及其装置，以在具有多个天线的无线通信系统中执行粗略增益控制环路，并且另外执行详细的增益控制环路以接收经过增益 控制过程，从而获得稳定的收益。 RF（Radio Frequency：射频）接收机110通过多个天线接收多个第一信号，并对接收到的第一信号进行增益控制，以输出第一信号作为多个第二信号。 如果大于阈值的第二信号的数量大于预定数量，则信号饱和度传感器（400）输出饱和状态确定值。 增益控制器（300）通过比较第二信号的功率来检测一个功率，并且将检测到的功率和基于饱和状态确定值确定的增益确定值输出到RF接收器（110）。