公开(公告)号：JPH01219659A

公开(公告)日：1989-09-01

申请号：JP4681388

申请日：1988-02-29

Applicant: TOSHIBA CORP

Inventor： KOYAMA MASAO ,  SAKAI TADASHI

IPC: G01N27/00 ,  H01L29/78

Abstract: PURPOSE:To make the title sensor small in size, to improve the reliability and to facilitate handling thereof, by a construction wherein an electrode for giving a reference potential is provided in a channel of a solution to be detected in a circulation-type cell. CONSTITUTION:A channel 2 of a solution to be detected is formed inside a flow cell wall material 1, and a field effect type element 3 is mounted by bonding in a part of the wall material 1. The sensitive part of the element 3 is so disposed as to form the same surface with the wall surface of the channel 2 and to be in contact with the solution to be detected, while the connecting part thereof with conductors is sealed up with an insulating material. In addition, a gold electrode 4 is bonded as a reference electrode on another part of the wall material 1, and it is disposed so that one surface thereof forms substantially the same surface with the wall of the channel 2 and is in contact with the solution to be detected. The potential of an input/output electrode of the element 3 is controlled in relation to the electrode 4.

公开(公告)号：JPS6478140A

公开(公告)日：1989-03-23

申请号：JP23477387

申请日：1987-09-21

Applicant: TOSHIBA CORP

Inventor： SAKAI TADASHI

IPC: G01N27/00

Abstract: PURPOSE:To improve the deterioration of an element caused by the infiltration of a solution into an electrode by using an FET type element where a gate contact electrode is provided on the opposite side of a chip, as a detecting part. CONSTITUTION:On an ISFET chip mounted to a flow cell, a drain contact pad 11, a source contact pad 12, an induction gate part 14, a silicon substrate 15, etc., are provided. In this state, by using an element where a gate and an electrode are arranged on the reverse side and the surface, a distance between the gate brought into directly contact with a solution, and the electrode whose contact with the solution is inhibited is extended, it is reduced to paint finely a resin to one and the same plane, and molding is facilitated. Also, even if the solution infiltrates through the interface of the mold, it scarcely reaches the electrode. Moreover, by constituting this sensor so that no current flows from other art than the electrode, even if the solution infiltrates other part than the electrode, for instance, the end face of a chip, the sensor is not broken down.

公开(公告)号：JPS6270505A

公开(公告)日：1987-04-01

申请号：JP21010285

申请日：1985-09-25

Applicant: TOSHIBA CORP

Inventor： KANAI HIDEYUKI ,  SAKAI TADASHI

IPC: B22F9/22

Abstract: PURPOSE:To stably produce hyperfine metallic particles having a uniform particle size distribution by forming a thin metallic oxide film on a substrate and reducing the metallic oxide. CONSTITUTION:A thin metallic oxide film of

公开(公告)号：JPS61191962A

公开(公告)日：1986-08-26

申请号：JP3312085

申请日：1985-02-20

Applicant: TOSHIBA CORP ,  UMETANI YOJI

Inventor： SAKAI TADASHI ,  KATSURA MASAKI ,  YONEHARA EISAKU ,  SHINPO MASARU ,  UMETANI YOJI

IPC: B01D15/08 ,  G01N30/60

Abstract: PURPOSE:To achieve a small size and a higher mechanical strength of a column, by providing an Si base body to make a column. CONSTITUTION:A spiral groove 11 is formed on the surface of a first Si base body 10 and an introduction hole 12 and a discharge hole 13 are formed at the initial and final ends of the groove 11 piercing the Si base body 10. First and second Si bodies 10 and 20 are joined together directly using no adhesive. Thus, a smaller size and a higher mechanical strength can be achieved.

公开(公告)号：JPS61191955A

公开(公告)日：1986-08-26

申请号：JP3310185

申请日：1985-02-20

Applicant: TOSHIBA CORP

Inventor： SAKAI TADASHI ,  KATSURA MASAKI ,  HIRAKI HIDEAKI

IPC: G01N27/00 ,  G01N27/12 ,  G01N27/30 ,  G01N27/414 ,  H01L21/18 ,  H01L29/78

Abstract: PURPOSE:To obtain a sensor suitable for volume production at a low cost, by forming a plurality of sensor elements on an Si substrate separately after the Si substrate is joined on the surface of a base body without the use of an adhesive. CONSTITUTION:An Si substrate is adhered is adhered on to the tip surface of an Si base body 11 with the surface thereof machined flat in a clean atmosphere, joined together directly through a SiO2 film 13 by heating up to higher than 200 deg.C and then, a plurality of sensors are formed on the Si substrate 12 separately. Then, the Si portion is removed except for the area where the sensor elements were formed and the exposed surface of the Si substrate is covered with an insulation film 17 for passivation made of Si3N4 or the like. The base body 11 is divided into respective sensor elements by dicing. This enables the passivation of the entire elements without any special process such as outline machining thereof to achieve the complete insulation without exposing Si of the elements to the cut section.

公开(公告)号：JPS61191038A

公开(公告)日：1986-08-25

申请号：JP3310285

申请日：1985-02-20

Applicant: TOSHIBA CORP

Inventor： SAKAI TADASHI ,  KATSURA MASAKI

IPC: H01L21/306

Abstract: PURPOSE:To obtain an Si cavity structure sealed by means of a thin film section by a method wherein the first Si substrate on which a concave section is formed and the second Si substrate on which a thin film layer formed are heated closely in contact with each other, and the second substrate is etched until the thin film layer is exposed. CONSTITUTION:A surface of the first Si substrate 10 is ground and a concave section is formed on the ground surface side. A sensor 12 is formed on the bottom of the concave section 11. A surface of the second Si substrate 20 is ground and a thin film layer 21 is formed on the ground surface to perform the junction. The surface of the substrate 10 and 20 are hydrophilic and the substrate 10 is contacted closely with the substrate 20, and then they are joined by heating at 200 deg.C in such a state. The substrate 20 is etched until the thin film layer 21 is exposed on the back of the substrate 20. Thereby, an Si cavity structure is obtained being sealed by means of the thin film layer 21.

公开(公告)号：JP2015050209A

公开(公告)日：2015-03-16

申请号：JP2013178713

申请日：2013-08-29

Applicant: 株式会社東芝 ,  Toshiba Corp

Inventor： SAITO TATSURO ,  WADA MAKOTO ,  ISOBAYASHI ATSUNOBU ,  KAJITA AKIHIRO ,  MIYAZAKI HISAO ,  SAKAI TADASHI

IPC: H01L21/768 ,  B82Y30/00 ,  B82Y40/00 ,  C01B31/02 ,  H01L23/522 ,  H01L29/06

CPC classification number: H01L21/76877 ,  H01L21/28556 ,  H01L23/5226 ,  H01L23/53276 ,  H01L2221/1094 ,  H01L2924/0002 ,  Y10S977/754 ,  Y10S977/932 ,  H01L2924/00

Abstract: 【課題】中空構造のCNTに安定して元素ドーピングを行うことができ、CNTを用いた配線の更なる低抵抗化をはかる。【解決手段】 CNTビアを用いた半導体装置であって、基板に設けたコンタクトビア用溝の底面に形成されたCNT成長のための触媒層32と、触媒層32が形成されたコンタクトビア用溝内に複数本のCNT33を埋め込んで形成されたCNTビア30と、を具備している。そして、CNT33は、複数のグラフェン層をコンタクトビア用溝の深さ方向から傾けた状態で積層して形成され、且つ側壁にグラフェン層の末端が露出するように形成されている。さらに、CNT33の側壁から該CNT33中に少なくとも1種類の元素がドーピングされている。【選択図】図1

Abstract translation: 要解决的问题：为了使具有中空结构的CNT稳定的元素添加以实现使用CNT的布线的较低电阻。解决方案：使用CNT通孔的半导体器件包括：用于CNT生长的催化剂层32，其形成在 设置在基板上的接触通孔槽的底面; 以及通过在形成有催化剂层32的沟槽中埋入多个CNT 33而形成的CNT通孔30。 CNT 33通过在从接触通孔槽的深度方向倾斜的状态下层叠多个石墨烯层而形成，以形成侧壁上的石墨烯层的端子。 此外，至少一个元件从CNT 33的侧壁掺杂到CNT 33中。

公开(公告)号：JP2015032662A

公开(公告)日：2015-02-16

申请号：JP2013160562

申请日：2013-08-01

Applicant: 株式会社東芝 ,  Toshiba Corp

Inventor： WADA MAKOTO ,  KAJITA AKIHIRO ,  ISOBAYASHI ATSUNOBU ,  SAITO TATSURO ,  SAKAI TADASHI ,  ISHIKURA TAISHI

IPC: H01L21/3205 ,  H01L21/027 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/544 ,  H01L21/76841 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53276 ,  H01L2221/1094 ,  H01L2223/54426 ,  H01L2223/5446 ,  H01L2924/0002 ,  H01L2924/00

Abstract: 【課題】CNTビアと上層配線との正確な合わせ精度を確保することができ、CNTビアを用いた多層配線構造の信頼性向上をはかる。【解決手段】下層配線を有する半導体基板10のデバイス領域上に、下層配線とコンタクトするように形成されたCNTビア構造と、基板10のマーク形成領域上に形成された、CNT43の埋め込みによる第1の合わせマークと、CNTビア構造及び第1の合わせマークを有する基板10上に形成され、CNTビア構造とオーミックコンタクトし、アライメント光を透過可能なコンタクト層51と、マーク形成領域上に形成された、CNT43を有しない第2の合わせマークと、CNTビア構造、第1の合わせマーク、及び第2の合わせマークを有する基板10上に形成され、CNTビア構造に電気的に接続された上層配線53と、を具備した。【選択図】図1

Abstract translation: 要解决的问题：确保CNT通孔和上层布线之间的精确对准，并提高使用CNT通孔的多层布线结构的可靠性。解决方案：半导体器件包括：形成在半导体衬底的器件区域上的CNT通孔结构 10具有较低层布线以便接触下层布线; 第一对准标记，其形成在基板10的标记形成区域上，并且通过嵌入CNT 43形成; 形成在具有CNT通孔结构的基板10上的接触层51和第一对准标记，并与CNT通孔结构形成欧姆接触并能够传输取向光; 形成在标记形成区域上并且没有CNT 43的第二对准标记; 以及形成在具有CNT通孔结构的基板10上的上层布线53，第一对准标记和第二对准标记，并且电连接到CNT通孔结构。

公开(公告)号：JP2014196939A

公开(公告)日：2014-10-16

申请号：JP2013072255

申请日：2013-03-29

Applicant: 株式会社東芝 ,  Toshiba Corp

Inventor： YAMAZAKI YUICHI ,  SAKAI TADASHI

IPC: G01N21/27

Abstract: 【課題】実施形態は、CNT検査に関するものである。【解決手段】実施形態の検査システムは、基板を配置する試料台と、基板に検査光を照射する光源と、検査光の反射光を受光するセンサと、センサが受光したスペクトルを解析する制御演算部と、制御演算部が解析した情報を保存する記憶装置とを備え、制御演算部は、カーボンナノチューブを設けた基準試料となる基板とカーボンナノチューブを設けた測定試料となる基板に検査光を照射して反射した反射スペクトルを測定し、制御演算部は、反射光スペクトルからピークを抽出し、制御演算部は、基準試料となる基板のあらかじめ測定した反射光スペクトルのピーク高さまたはピーク面積と、カーボンナノチューブの高さまたは密度と相関する関数と測定試料の反射光スペクトルのピーク高さまたはピーク面積から、測定試料のカーボンナノチューブの長さまたは密度を見積もることを特徴とする。【選択図】図2

Abstract translation: 要解决的问题：提供CNT检查。一种实施方式的检查系统包括：样品台，其上布置有基板;光源，其用检查光照射所述基板; 接收检查光的反射光的传感器; 分析传感器接收的频谱的控制操作部分; 以及存储装置，其存储控制操作部分析的信息。 控制操作部照射作为具有碳纳米管的参考样品的基板和作为具有检查光的设置有碳纳米管的测量样品的基板，并测量反射光谱。 控制操作部分从反射光谱中提取峰值，并且控制操作部分基于测量样品的碳纳米管的长度或密度，基于先前测量的基板的反射光谱的峰高或峰值面积 作为参考样品，将碳纳米管的高度或密度与测量样品的反射光谱的峰值高度或峰面积相关联的函数。

公开(公告)号：JP2014127646A

公开(公告)日：2014-07-07

申请号：JP2012284912

申请日：2012-12-27

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： YAMAZAKI YUICHI ,  SAKAI TADASHI

IPC: H01L21/3205 ,  C01B31/02 ,  C01B31/04 ,  C23C16/02 ,  C23C16/26 ,  H01L21/285 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76877 ,  B82Y40/00 ,  C01B32/16 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/76831 ,  H01L21/76844 ,  H01L21/76862 ,  H01L21/76876 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/53276 ,  H01L2221/1094 ,  H01L2924/0002 ,  Y10S977/742 ,  Y10S977/762 ,  Y10S977/842 ,  Y10S977/843 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To suppress CNT growth from an outermost surface.SOLUTION: A method for manufacturing wires concerned with this embodiment includes: a step for forming a via to be penetrated into an interlayer insulating film of a member provided with the interlayer insulating film on a substrate; a step for forming a ground wiring film on the via; a step for removing the ground wiring film from the bottom of the via; a step for forming a catalyst metallic inactive film on the ground wiring film; a step for removing the catalyst metallic inactive film from the bottom of the via; a step for forming a catalyst metallic film on the via bottom from which the catalyst metallic inactive film is removed; a step for applying first plasma processing and second plasma processing using gas including no carbon to a member on which the catalyst metallic film is formed; a step for forming a graphite layer on the catalyst metallic film after the plasma processing step; and a step for allowing a carbon nanotube to grow from the catalyst metallic film on which the graphite layer is formed: in which plasma gas pressure of the first plasma processing is higher than gas pressure of the second plasma processing.

Abstract translation: 要解决的问题：从最外表面抑制CNT的生长。解决方案：本实施例涉及的制造线的方法包括：形成通孔的步骤，该通孔被穿入设置有层间绝缘膜的部件的层间绝缘膜 在基材上 在所述通孔上形成接地布线膜的步骤; 用于从所述通孔的底部去除所述接地布线膜的步骤; 在接地布线膜上形成催化剂金属惰性膜的工序; 从通孔的底部除去催化剂金属惰性膜的步骤; 在去除催化剂金属惰性膜的通孔底部形成催化剂金属膜的步骤; 使用不含碳的气体的第一等离子体处理和第二等离子体处理到其上形成有催化剂金属膜的构件的步骤; 在等离子体处理步骤之后在催化剂金属膜上形成石墨层的步骤; 以及使第一等离子体处理的等离子体气体压力高于第二等离子体处理的气体压力的从形成有石墨层的催化剂金属膜生长碳纳米管的工序。