公开(公告)号：US10332889B2

公开(公告)日：2019-06-25

申请号：US15951194

申请日：2018-04-12

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Ger-Pin Lin ,  Tien-Chen Chan ,  Shu-Yen Chan ,  Chi-Mao Hsu ,  Shih-Fang Tzou ,  Ting-Pang Chung ,  Chia-Wei Wu

IPC: H01L21/00 ,  H01L27/108 ,  H01L21/02 ,  H01L21/324 ,  H01L21/48 ,  H01L21/762

Abstract: A method of manufacturing a semiconductor device is provided, which includes the steps of providing a capacitor structure, forming a conductive layer on the capacitor structure, performing a hydrogen doping process to the conductive layer, forming a metal layer on the conductive layer after the hydrogen doping process, and patterning the metal layer and the conductive layer to forma top electrode plate.

公开(公告)号：US20190189620A1

公开(公告)日：2019-06-20

申请号：US16177348

申请日：2018-10-31

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Hsu-Yang Wang ,  Ping-Cheng Hsu ,  Shih-Fang Tzou ,  Chin-Lung Lin ,  Yi-Hsiu Lee ,  Koji Taniguchi ,  Harn-Jiunn Wang ,  Tsung-Ying Tsai

IPC: H01L27/108 ,  H01L21/762 ,  H01L21/308

CPC classification number: H01L27/10885 ,  H01L21/3086 ,  H01L21/76224 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10891

Abstract: A method for forming a memory device is disclosed, including providing a substrate, forming an isolation structure and plural active regions in the substrate, forming a plurality of island features on the substrate respectively covering two of the terminal portions of the active regions, using the island features as an etching mask to etch the substrate to perform a first etching process to define a first recessed region and plural island structures on the substrate. The island structures respectively comprise the two terminal portions of the active regions and the first recessed region comprises the central portions of the active regions.

公开(公告)号：US10249706B1

公开(公告)日：2019-04-02

申请号：US15951185

申请日：2018-04-12

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Chia-Lung Chang ,  Wei-Hsin Liu ,  Po-Chun Chen ,  Yi-Wei Chen ,  Han-Yung Tsai ,  Tzu-Chin Wu ,  Shih-Fang Tzou

IPC: H01L49/02 ,  H01L27/108

Abstract: The present invention provides a semiconductor structure comprising a substrate, a cell region defined on the substrate, a plurality of lower electrodes of the capacitor structures located in the cell region, an top support structure, contacting a top region of the lower electrode structure, and at least one middle support structure located between the substrate and the top support structure, contacting a middle region of the lower electrode structure, wherein when viewed in a top view, the top support structure and the middle support structure do not completely overlapped with each other.

公开(公告)号：US20190081047A1

公开(公告)日：2019-03-14

申请号：US16052636

申请日：2018-08-02

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Li-Wei Feng ,  Shih-Fang Tzou ,  Chien-Cheng Tsai ,  Chih-Chi Cheng ,  Chia-Wei Wu ,  Ger-Pin Lin

IPC: H01L27/108

Abstract: A semiconductor device and method of manufacturing the same is provided in the present invention. The method includes the step of forming first mask patterns on a substrate, wherein the first mask patterns extend in a second direction and are spaced apart in a first direction to expose a portion of first insulating layer, removing the exposed first insulating layer to form multiple recesses in the first insulating layer, performing a surface treatment to the recess surface, filling up the recesses with a second insulating layer and exposing a portion of the first insulating layer, removing the exposed first insulating layer to form a mesh-type isolation structure, and forming storage node contact plugs in the openings of mesh-type isolation structure.

公开(公告)号：US20180337187A1

公开(公告)日：2018-11-22

申请号：US16028364

申请日：2018-07-05

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Chih-Chieh Tsai ,  Pin-Hong Chen ,  Tzu-Chieh Chen ,  Tsun-Min Cheng ,  Yi-Wei Chen ,  Hsin-Fu Huang ,  Chi-Mao Hsu ,  Shih-Fang Tzou

IPC: H01L27/108

Abstract: A semiconductor structure for preventing row hammering issue in DRAM cell is provided in the present invention. The structure includes a trench with a gate dielectric, an n-type work function metal layer, a TiN layer conformally formed within, and a buried word line filled in the trench.

公开(公告)号：US20180247943A1

公开(公告)日：2018-08-30

申请号：US15889182

申请日：2018-02-05

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Li-Wei Feng ,  Shih-Fang Tzou ,  Chien-Ting Ho ,  Ying-Chiao Wang ,  Yu-Ching Chen ,  Hui-Ling Chuang ,  Kuei-Hsuan Yu

IPC: H01L27/108

CPC classification number: H01L27/10855 ,  H01L27/10814 ,  H01L27/10823

Abstract: A semiconductor structure with a capacitor landing pad includes a substrate. A capacitor contact plug is disposed on the substrate. A capacitor landing pad contacts and electrically connects the capacitor contact plug. A bit line is disposed on the substrate. A dielectric layer surrounds the capacitor landing pad. The dielectric layer includes a bottom surface lower than a top surface of the bit line.

公开(公告)号：US20180226470A1

公开(公告)日：2018-08-09

申请号：US15873913

申请日：2018-01-18

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Ger-Pin Lin ,  Tien-Chen Chan ,  Shu-Yen Chan ,  Chi-Mao Hsu ,  Shih-Fang Tzou

IPC: H01L49/02 ,  H01L27/108

CPC classification number: H01L28/84 ,  H01L27/10808 ,  H01L27/10852 ,  H01L28/90 ,  H01L28/91

Abstract: A method of fabricating a bottom electrode includes providing a dielectric layer. An atomic layer deposition is performed to form a bottom electrode material on the dielectric layer. Then, an oxidation process is performed to oxidize part of the bottom electrode material. The oxidized bottom electrode material transforms into an oxide layer. The bottom electrode material which is not oxidized becomes a bottom electrode. A top surface of the bottom electrode includes numerous hill-like profiles. Finally, the oxide layer is removed.

公开(公告)号：US10043811B1

公开(公告)日：2018-08-07

申请号：US15627455

申请日：2017-06-20

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Chih-Chieh Tsai ,  Pin-Hong Chen ,  Tzu-Chieh Chen ,  Tsun-Min Cheng ,  Yi-Wei Chen ,  Hsin-Fu Huang ,  Chi-Mao Hsu ,  Shih-Fang Tzou

IPC: H01L27/108

Abstract: A semiconductor structure for preventing row hammering issue in DRAM cell is provided in the present invention. The structure includes a trench with a gate dielectric, an n-type work function metal layer, a TiN layer conformally formed within, and a buried word line filled in the trench.

公开(公告)号：US20180190658A1

公开(公告)日：2018-07-05

申请号：US15859766

申请日：2018-01-02

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Mei-Ling Chen ,  Wei-Hsin Liu ,  Yi-Wei Chen ,  Chia-Lung Chang ,  Jui-Min Lee ,  Ching-Hsiang Chang ,  Tzu-Chin Wu ,  Shih-Fang Tzou

IPC: H01L27/108 ,  H01L21/768 ,  H01L21/02

CPC classification number: H01L21/76834 ,  H01L21/02112 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/02348 ,  H01L21/76825 ,  H01L21/823475 ,  H01L27/10817 ,  H01L27/10823 ,  H01L27/10852 ,  H01L27/10894 ,  H01L27/10897 ,  H01L28/87 ,  H01L28/91

Abstract: The present invention provides a method for fabricating a semiconductor device, comprising at least the steps of: providing a substrate in which a memory region and a peripheral region are defined, the memory region includes a plurality of memory cells, each memory cell includes at least a first transistor and a capacitor, the peripheral region compress a second transistor, a first insulating layer is formed within the memory region and the peripheral region by an atomic layer deposition process, covering the capacitor of the memory cells in the memory region and the second transistor in the peripheral region, and a second insulating layer is formed, overlying the first insulating layer and the peripheral region. Finally, a contact structure is formed within the second insulating layer, and electrically connecting the second transistor.

公开(公告)号：US09825144B2

公开(公告)日：2017-11-21

申请号：US15644850

申请日：2017-07-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Fang Tzou ,  Chien-Ming Lai ,  Yi-Wen Chen ,  Hung-Yi Wu ,  Tong-Jyun Huang ,  Chien-Ting Lin ,  Chun-Hsien Lin

IPC: H01L29/76 ,  H01L29/49 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/423

CPC classification number: H01L29/4966 ,  H01L21/823842 ,  H01L21/823864 ,  H01L29/42364 ,  H01L29/66545

Abstract: A metal gate transistor includes a substrate, a metal gate on the substrate, and a source/drain region in the substrate adjacent to the metal gate. The metal gate includes a high-k dielectric layer, a bottom barrier metal (BBM) layer comprising TiSiN on the high-k dielectric layer, a TiN layer on the BBM layer, a TiAl layer between the BBM layer and the TiN layer, and a low resistance metal layer on the TiN layer.