Abstract:
A protective insulating film is deposited over first and second field-effect transistors formed on a semiconductor substrate. A capacitor composed of a capacitor lower electrode, a capacitor insulating film composed of an insulating metal oxide film, and a capacitor upper electrode is formed on the protective insulating film. A first contact plug formed in the protective insulating film provides a direct connection between the capacitor lower electrode and an impurity diffusion layer of the first field-effect transistor. A second contact plug formed in the protective insulating film provides a direct connection between the capacitor upper electrode and an impurity diffusion layer of the second field-effect transistor.
Abstract:
A holder 6 having a funnel-shaped portion is provided above an eyelet 5, and a conductive metal piece 11 is supplied to the vicinity of a portion at which plasma arc welding is performed in the funnel-shaped portion. The conductive metal piece 11 is fused together by plasma arc welding so that the hole 9 of the eyelet is closed completely. Thus, the lead wire 8 can be connected firmly. Therefore, even if the hole diameter of the eyelet is excessively large relative to the diameter of the lead wire, complete closure and sufficient fusion connection can be achieved.
Abstract:
[Problem] To prevent a void from being formed in a CMOS inverter due to electromigration. [Means for Solving the Problem] A power line 11 is connected to the source of a p-channel MOS transistor Tr1 via a first contact 12. A ground line 13 is connected to the source of an n-channel MOS transistor Tr2 via a second contact 14. One terminal of a first output signal line 15 is connected to the drain of the p-channel MOS transistor Tr1 via a third contact 16, while the other terminal thereof is connected to the drain of the n-channel MOS transistor Tr2 via a fourth contact 17. One terminal of a second output signal line 18 is connected to the fourth contact 17, while the other terminal thereof extends toward the output terminal of the inverter. A first path of an input signal line 19 is connected to the gate electrode 20 of the p-channel MOS transistor Tr1 via a fifth contact 21 , while a second path thereof is connected to the gate electrode 20 of the n-channel MOS transistor Tr2 via a sixth contact 22.
Abstract:
After adhesive resin (46) is applied to a surface of a flat panel (42), a front panel (43) is glued thereto. One side of the front panel (43) is contacted to the adhesive resin layer (46) with the front panel (43) tilted toward the surface of the flat panel (42). Then, the front panel (43) is moved slowly to be close and parallel to the flat panel (42). Finally, the front panel (43) is pressed to the surface of the flat panel (42). Afterward, the adhesive resin (46) is hardened. It is preferable that the thickness of the adhesive resin (46) applied to the surface of the flat panel (42) is decreasing from the side to which the side of the front panel (43) is contacted, to the opposite side. By the above-mentioned method, an image display apparatus having multilayer structure comprising of a flat panel (42) for displaying image, an adhesive resin layer (46) and a front panel (43) can be manufactured efficiently.
Abstract:
A metal halide lamp has a long life since the temperature of the electrodes can be prevented from excessively rising. The metal halide lamp has an arc tube 3 that is composed of a light emitting part 1 and a sealing part 2 at each end of the light emitting part 1. A pair of electrodes 4 are extended from the ends of the arc tube 3 into the discharge chamber of the light emitting part 1 so that the discharge side ends of the electrodes 4 face each other. The other end of each electrode 4 is connected to a conductor 5 sealed in the sealing part 2. A part of the electrode 4, sealed in the sealing part 2, from the boundary between the light emitting part 1 and the sealing part 2 to the discharge side end of the conductor 5 is referred to as the electrode sealing part L. A metal member 7 partially covers the electrode sealing part L. The ratio of the weight A (mg) of the metal member 7 to the weight B (mg) of the electrode sealing part L is defined as an inequality 0.2≤A/B≤1.6 .
Abstract:
This invention provides a display apparatus having high accuracy to control automatically power consumed for display operation suitable for emission-type display apparatus like a plasma display apparatus, electroluminescence display apparatus and a light emission diode display apparatus. The display apparatus comprises an emission unit (27), integrating circuits (11, 12, 13) for integrating input picture signals of R, G and B for each predetermined period to output average levels of R signal, G signal and B signal, respectively, multiplying circuits (14, 15, 16) for multiplying those average levels by their respective parameters KR, KG and KB, respectively, an adder (17) for obtaining a signal indicating expected consumption power on the emission unit by adding output signals from the multiplying circuits, a controller (18) for receiving the power prediction signal to output a control signal based on the received signal, and a brightness control circuit for controlling light emission amount per unit area according to the control signal.
Abstract:
By displaying the video signal in the display unit only, the detecting intensity of signal stored actually in the memory (signal storing means) is not known, and it is difficult to adjust the appropriate irradiation illuminance and lens, and it is hence an object to present an optical information reader and an optical information reading system capable of expressing the detecting intensity as waveform in the display unit. The data of the specified line is picked up (step 11), and transformed into waveform of detecting intensity, and shown in the display unit (step 12).
Abstract:
A gas discharge panel in which cells filled with a discharge gas are arranged as a matrix between a pair of opposed plates, and in which a pair of display electrodes on a surface of one of the pair of opposed plates extend across a plurality of cells in the direction of rows, where a gap between the pair of display electrodes has two discharge gap widths one of which is larger than the other. The voltage is lowered and the power consumption is properly restricted by starting the discharge at the discharge gap at a space having the smaller gap width. An excellent discharge efficiency is secured by sustaining the discharge at a space having the larger gap width.
Abstract:
The present invention is aimed at providing an optical disk (201a), an optical disk device, and an optical disk reproduction method, for allowing for stable and efficient reading of address information. The optical disk (201a) includes a plurality of tracks (201b) each divided into a plurality of recording sectors (201c). Each of the recording sectors (201c) includes a header region (202). The header region (202) includes address information (ID) for identifying the position of the corresponding recording sector (201c) and address synchronous information (AM) for identifying the recording position of the address information (ID) for bit synchronization. The address information (ID) has been modulated using a run length limit code of a maximum inversion interval of T max bits (T max is a natural number), and the address synchronous information (AM) includes two patterns of which inversion interval is (T max + 3) bits or more, so that the reproduced signal of the address synchronous information (AM) is distinguished from the reproduced signal of other information.
Abstract:
The present invention is aimed at providing an optical disk, an optical disk device, and an optical disk reproduction method, for allowing for stable and efficient reading of address information. The optical disk includes a plurality of tracks each divided into a plurality of recording sectors. Each of the recording sectors includes a header region (52). The header region (52) includes address information (ID 1...4) for identifying the position of the corresponding recording sector and address synchronous information (AM) for identifying the recording position of the address information for bit synchronization. The address information (ID) has been modulated using a run length limit code of a maximum inversion interval of T max bits (T max is a natural number), and the address synchronous information (AM) includes two patterns of which inversion interval is (T max + 3) bits or more, so that the reproduced signal of the address synchronous information (AM) is distinguished from the reproduced signal of other information.