公开(公告)号：US20020109554A1

公开(公告)日：2002-08-15

申请号：US10021282

申请日：2001-10-30

Applicant: STMicroelectronics S.A.

Inventor： Bruno Gailhard ,  Olivier Ferrand

IPC: H03B001/00

CPC classification number: H03L7/0997 ,  G06F1/08

Abstract: A generator includes an oscillator for producing a clock signal from an N-bit control number. The oscillator includes a first group of cells, with each cell including at least one series connected inverter. A first selection circuit selects a variable number of the cells as a function of the most significant bits of the control number. The oscillator also includes a second group of cells, with each cell including at least one series connected inverter. A second selection circuit selects one of the cells as a function of the least significant bits of the control number. The selected cells of the first and second groups of cells are series connected to form a chain of inverters.

Abstract translation: 发生器包括用于从N位控制编号产生时钟信号的振荡器。 振荡器包括第一组单元，每个单元包括至少一个串联的反相器。 第一选择电路根据控制数的最高有效位选择可变数目的单元。 振荡器还包括第二组单元，每个单元包括至少一个串联连接的反相器。 第二选择电路根据控制号的最低有效位选择一个单元。 第一和第二组电池的所选择的电池被串联连接以形成一个反相器链。

公开(公告)号：US20020097093A1

公开(公告)日：2002-07-25

申请号：US10020010

申请日：2001-12-13

Applicant: STMicroelectronics S.A.

Inventor： Jerome Bourgoin ,  Frederic Goutti

IPC: H03F003/45

CPC classification number: H03G1/0035

Abstract: An amplifier includes an input stage with one or more input terminals for receiving a signal to be amplified, and an output terminal. An inverting gain stage includes an input terminal connected to the output terminal of the input stage, an output terminal for delivering an amplified signal, and a variable feedback resistor connected between the output terminal and input terminal thereof. The input stage is a transconductor stage biased by a current source. A transconductance thereof is set by a resistor of the current source so that the amplifier has a gain proportional to the product of the variable feedback resistor multiplied by the transconductance.

Abstract translation: 放大器包括具有用于接收要放大的信号的一个或多个输入端的输入级和输出端。 反相增益级包括连接到输入级的输出端的输入端，输出放大信号的输出端和连接在输出端和输入端之间的可变反馈电阻。 输入级是由电流源偏置的跨导级。 其跨导由电流源的电阻器设置，使得放大器具有与可变反馈电阻乘以跨导的乘积成比例的增益。

公开(公告)号：US20020093589A1

公开(公告)日：2002-07-18

申请号：US10032333

申请日：2001-12-18

Applicant: STMicroelectronics S.A.

Inventor： Arnaud Albella ,  Vincent Tauzia

IPC: H04N007/00 ,  H04N011/00

CPC classification number: H04N7/0882 ,  H04H60/27

Abstract: A method for storing pages of a teletext service, with at least one page being received by a storage circuit of a television receiver, is provided. The storage circuit includes a data memory for storing the at least one received page. The method includes extracting a reference number from the at least one received page, checking whether the at least one received page is a requested page, and evaluating contents of the data memory to decide whether the at least one received page is to be stored as a function of free space in the data memory and an importance of the at least one received page. The method also includes storing the at least one received page if it is decided that the at least one received page is to be stored.

Abstract translation: 一种用于存储图文电视服务的页面的方法，其中至少一个页面被电视接收机的存储电路接收。 存储电路包括用于存储至少一个接收页面的数据存储器。 该方法包括从至少一个接收到的页面提取参考号码，检查至少一个接收的页面是否是所请求的页面，以及评估数据存储器的内容，以决定是否将至少一个接收到的页面存储为 数据存储器中的可用空间的功能以及至少一个接收页面的重要性。 如果确定要存储至少一个接收到的页面，则该方法还包括存储至少一个接收到的页面。

公开(公告)号：US20020082791A1

公开(公告)日：2002-06-27

申请号：US10025372

申请日：2001-12-19

Applicant: STMicroelectronics S.A.

Inventor： Francois Tailliet

IPC: G06F019/00 ,  G01R035/00

CPC classification number: G11C29/028 ,  G11C7/1045 ,  G11C7/20 ,  G11C7/22 ,  G11C16/04 ,  G11C16/32 ,  G11C29/02 ,  G11C29/14 ,  G11C29/50 ,  G11C29/50012

Abstract: A method for adjusting a duration of an internal timing signal in an integrated circuit with a value close to a typical value of the duration may include activating the internal timing signal in the integrated circuit and sequentially sending calibration values to an input of the integrated circuit. The expiration of the internal timing signal may determine the last calibration value received or being received, and the calibration data may be applied to a device for adjusting the duration of the internal timing signal.

Abstract translation: 用于以接近于持续时间的典型值的值调整集成电路中的内部定时信号的持续时间的方法可以包括激活集成电路中的内部定时信号并且顺序地将校准值发送到集成电路的输入。 内部定时信号的到期可以确定接收或正在接收的最后一个校准值，并且校准数据可以应用于用于调整内部定时信号的持续时间的设备。

公开(公告)号：US20020081374A1

公开(公告)日：2002-06-27

申请号：US09902497

申请日：2002-01-15

Applicant: STMicroelectronics S.A.

Inventor： Didier Dutartre ,  Patrick Jerier

IPC: B05D005/12

CPC classification number: C30B29/06 ,  C23C16/24 ,  C30B25/20

Abstract: The present invention relates to a method of vapor phase epitaxial deposition of silicon on a silicon substrate including areas containing dopants at high concentration among which is arsenic, while avoiding an autodoping of the epitaxial layer by arsenic, including the steps of performing a first thin epitaxial deposition, then an anneal; the conditions and the duration of the first epitaxial deposition and of the anneal being such that the arsenic diffusion length is much lower than the thickness of the layer formed in the first deposition; and performing a second epitaxial deposition for a chosen duration to obtain a desired total thickness.

Abstract translation: 本发明涉及一种在硅基板上气相外延沉积硅的方法，该方法包括含有高浓度掺杂剂的区域，其中砷是砷，同时避免了砷的外延层的自掺杂，包括以下步骤：执行第一薄外延 沉积，然后退火; 第一外延沉积和退火的条件和持续时间使得砷扩散长度远低于在第一沉积中形成的层的厚度; 以及对所选择的持续时间进行第二外延沉积以获得期望的总厚度。

公开(公告)号：US20020076899A1

公开(公告)日：2002-06-20

申请号：US09920315

申请日：2001-08-01

Applicant: STMicroelectronics S.A.

Inventor： Thomas Skotnicki ,  Michel Haond ,  Didier Dutartre

IPC: H01L021/76

CPC classification number: H01L21/76264 ,  H01L21/76283

Abstract: Processes are provided for fabricating a substrate having a silicon-on-insulator (SOI) or silicon-on-nothing (SON) architecture, which are applicable to the manufacture of semiconductor devices, especially transistors such as those of the MOS, CMOS, BICMOS, and HCMOS types. In the fabrication processes, a multilayer stack is grown on a substrate by non-selective full-wafer epitaxy. The multilayer stack includes a silicon layer on a Ge or SiGe layer. Active regions are defined and masked, and insulating pads are formed so as to be located around the perimeter of each of the active regions at predetermined intervals and placed against the sidewalls of the active regions. The insulating trenches are etched, and the SiGe or Ge layer is laterally etched so as to form an empty tunnel under the silicon layer. The trenches are filled with a dielectric. In the case of an SOI archiutecture, the tunnel is filled with a dielectric.

Abstract translation: 提供了用于制造具有绝缘体上硅（SOI）或无硅（SON）结构的衬底的工艺，其可应用于半导体器件的制造，特别是诸如MOS，CMOS，BICMOS的晶体管 和HCMOS类型。 在制造工艺中，通过非选择性全晶片外延在衬底上生长多层叠层。 多层堆叠包括Ge或SiGe层上的硅层。 有源区被限定和掩蔽，并且绝缘垫被形成为以预定的间隔围绕每个有源区的周边定位并且抵靠有源区的侧壁放置。 绝缘沟槽被蚀刻，SiGe或Ge层被横向蚀刻，以便在硅层下方形成一个空洞。 沟槽填充有电介质。 在SOI结构的情况下，隧道填充有电介质。

公开(公告)号：US20020031848A1

公开(公告)日：2002-03-14

申请号：US09898523

申请日：2001-07-03

Applicant: STMicroelectronics S.A.

Inventor： Emmanuel Perrin ,  Herve Jaouen

IPC: H01L021/66 ,  H01L021/302 ,  H01L021/461 ,  G01R031/26

CPC classification number: B24B37/013 ,  B24B37/042 ,  B24B49/03 ,  B24B49/16 ,  H01L21/31053

Abstract: A method of determining the time for polishing the surface of an integrated circuit wafer on a polishing machine. A sample wafer is fabricated to include at least one high plateau and at least one low plateau joined by a sudden transition. At least one initial profile is topographically scanned, and the surface of the sample wafer is polished at a particular polishing pressure for a particular polishing time. The final profile of the polished layer is topographically scanned in the corresponding area, and the initial and final topographical scans of the sample wafer are converted into Fourier series. The surface of the wafer to be polished is topographically scanned, and the topographic scan of the wafer to be polished is converted into a Fourier series. The time for polishing the wafer to be polished is calculated from the Fourier series and the average thickness to be removed.

Abstract translation: 确定在抛光机上抛光集成电路晶片的表面的时间的方法。 制造样品晶片以包括至少一个高平台和至少一个通过突然过渡连接的低平台。 至少一个初始轮廓被地形扫描，并且在特定抛光压力下抛光样品晶片的表面以达到特定的抛光时间。 将抛光层的最终轮廓在相应的区域进行地形扫描，并将样品晶片的初始和最终的地形扫描转换为傅立叶级数。 将待研磨的晶片的表面进行地形扫描，并将要抛光的晶片的地形扫描转换为傅立叶级数。 抛光抛光晶片的时间由傅立叶级数和要去除的平均厚度计算。

公开(公告)号：US20020030515A1

公开(公告)日：2002-03-14

申请号：US09808744

申请日：2001-03-15

Applicant: STMicroelectronics S.A.

Inventor： Christophe Garnier

IPC: H03K005/22

CPC classification number: H03K5/2481 ,  H03F1/0244

Abstract: A device for comparing two input signals includes a first comparator with differential outputs to whose inputs the signals are applied. The first comparator is followed by a second comparator delivering an output logic signal of the device. Each comparator includes at least one input differential stage, and each stage has two arms biased by a bias current generator. The comparison device may also include at least one additional current supply circuit associated with an arm of the input differential stage of the first comparator to copy the current of the arm and add it, with a multiplier factor, to the bias current of the input differential stage of the second comparator. This facilitates a corresponding switch-over.

公开(公告)号：US20020027475A1

公开(公告)日：2002-03-07

申请号：US09886852

申请日：2001-06-21

Applicant: STMicroelectronics S.A.

Inventor： Didier Belot

IPC: H03F003/45

CPC classification number: H03F3/191 ,  H03F3/45089 ,  H03F2200/294 ,  H03F2200/372 ,  H03F2203/45316 ,  H03F2203/45386 ,  H03F2203/45554 ,  H03F2203/45704

Abstract: The amplifier includes an input amplifier stage, an output amplifier stage cascode-connected with the input amplifier stage, and a load stage connected to the output stage. The load stage includes a plurality of circuits each including a capacitive component and an inductive component having a Q greater than 10, and having respective different resonant frequencies. All the gain curves respectively associated with all the circuits have, to within a stated tolerance, the same maximum gain value at the resonant frequencies. The gain curves respectively associated with two circuits having respective immediately adjacent resonant frequencies overlap below a threshold 3 dB, to within a stated tolerance, below the maximum gain value.

Abstract translation: 放大器包括输入放大器级，与输入放大级级共源共栅放大器级的输出放大器级和连接到输出级的负载级。 负载级包括多个电路，每个电路包括电容分量和Q大于10的电感分量，并且具有各自不同的谐振频率。 分别与所有电路相关联的所有增益曲线在所述公差内具有在谐振频率下相同的最大增益值。 分别与具有相应的紧邻谐振频率的两个电路相关联的增益曲线重叠在阈值3dB以下，达到所述公差之内，低于最大增益值。

公开(公告)号：US20020017868A1

公开(公告)日：2002-02-14

申请号：US09770760

申请日：2001-01-25

Applicant: STMicroelectronics S.A.

Inventor： Jean-Pierre Blanc

IPC: H01J029/98

CPC classification number: H04N9/68 ,  H04N5/57 ,  H04N5/68 ,  H04N9/73

Abstract: A process for color adjustment of a color monitor including a cathode-ray tube and a brightness adjustment module includes providing a nominal brightness signal downstream of a white level adjustment module for adjusting a white level and upstream of a black level adjustment module for adjusting a black level. The process also includes setting a voltage required to obtain a black color image, setting a voltage required to obtain a white color image, providing the nominal brightness signal upstream of the white level adjustment module, and setting the voltage required to obtain the black color image.

Abstract translation: 包括阴极射线管和亮度调节模块的彩色监视器的颜色调整过程包括在白电平调节模块的下游提供用于调整白电平的标称亮度信号和用于调节黑色的黑电平调节模块的上游 水平。 该过程还包括设置获得黑色图像所需的电压，设置获得白色图像所需的电压，提供白平衡调节模块上游的标称亮度信号，以及设置获得黑色图像所需的电压 。