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公开(公告)号：KR1019940001838B1
公开(公告)日：1994-03-09
申请号：KR1019900018064
申请日：1990-11-09
Applicant: 삼성전자주식회사
Inventor： 김기범
IPC: H04N7/12
CPC classification number: H04N5/21
Abstract: The circuit splits video signal with the sequential and random signal to reduce the effect of transmission noise. The circuit includes a controller (20) including a sequential address signal generator (21) for generating sequential address signal and for delaying input horizontal synchronous signal, a random address signal generator (22) for generating random address signal, a first and, a second switch (23,24) for selecting a random address signal or sequential address signal according to the split control signal and inverted split control signal, and a signal converter (10) for recording input video signal on a RAM sequentially according to the split control signal and for reading out the video signal stored on another RAM randomly.
Abstract translation: 该电路用顺序和随机信号分割视频信号，以减少传输噪声的影响。 该电路包括一个控制器（20），它包括用于产生顺序地址信号和延迟输入水平同步信号的顺序地址信号发生器（21），用于产生随机地址信号的随机地址信号发生器（22），第一和第二 开关（23,24），用于根据分离控制信号和反相分离控制信号选择随机地址信号或顺序地址信号;以及信号转换器（10），用于根据分离控制信号顺序地将输入视频信号记录在RAM上 并随机读出存储在另一个RAM上的视频信号。
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公开(公告)号：KR1019930007279A
公开(公告)日：1993-04-22
申请号：KR1019910016129
申请日：1991-09-16
Applicant: 삼성전자주식회사
Inventor： 김기범
IPC: H04N21/4408 , H04N5/44
Abstract: 고화질 텔레비젼 시스템의 영상 데이터 전송장치에 관한 것으로, 특히 제한된 지상 채널을 통해 광대역의 고화질 디지털 영상데이타를 효율적으로 전송하는 디지털 영상 데이터 전송장치에 관한 것이다.
고화질 영상 데이터 전송 장치에서 제한된 지상 채널을 통해 광대역의 고화질 디지털 영상 데이터를 효율적으로 전송하기 위해 디지털 영상 데이터를 스크램블링하여 버스트 에러를 임펄스 노이즈가 되도록 한후 상기 임펄스 노이즈를 제거하여 전송한다.-
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Patent Agency Ranking
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公开(公告)号：KR1019910007809B1
公开(公告)日：1991-10-02
申请号：KR1019890004112
申请日：1989-03-30
Applicant: 삼성전자주식회사
Inventor： 김기범
IPC: H03K3/00
Abstract: The circuit is for compensating the distortion of digital data caused by the amplitude distortion and the timing delay. The circuit includes a comparator for comparing the states of the distorted input data and the compensated data to generate the digital data having constant amplitude, a clock generator for generating a second and a third clock signal by dividing the frequency of sampling data, a latch for synchronizing the output of the comparator to the first to the third clock signal, an operator for logical operation of the output signals of the latch, a selector for selecting the add or the multiplication operation according to the state of the digital data, and a transmitter for transmitting the compensated digital data by latching the output of the selector.
Abstract translation: 该电路用于补偿由幅度失真和定时延迟引起的数字数据失真。 该电路包括比较器，用于比较失真输入数据和补偿数据的状态以产生具有恒定幅度的数字数据;时钟发生器，用于通过除法采样数据的频率产生第二和第三时钟信号; 将比较器的输出同步到第一到第三时钟信号，操作器用于锁存器的输出信号的逻辑运算，用于根据数字数据的状态选择加法运算或乘法运算的选择器，以及发送器 用于通过锁存选择器的输出来发送补偿的数字数据。
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