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公开(公告)号：KR1019950020180A
公开(公告)日：1995-07-24
申请号：KR1019930028323
申请日：1993-12-17
IPC: G06F13/18
Abstract: 본 발명은, 동등한 레벨에서 먼저 버스사용권을 요구한 버스 마스타가 버스사용권을 사용할 수 있도록 하고, 간단한 로직으로 구현하여 비용절감의 효과를 갖는 우선 발생순 버스 사용권 중재회로를 제공하는데 그 목적이 있으며, 동일한 기능이나 지위의 버스마스타들을 여러개 인터이스할 경우 차별화된 우선순위 방식이 아닌 우선발생순으로 버스 사용권을 중재하는 회로를 구현하되 간단한 SR 플립플롭과 인버터 및 OR 게히트로 구성하여 경제성을 높였고, 우선 순위가 필요없는 같은 기능 및 지위의 버스 마스타들에게 효율적인 방식인 우선 발생순위 중재 방식이 가능하도록 하였다.
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公开(公告)号：KR1019950001507B1
公开(公告)日：1995-02-25
申请号：KR1019910026089
申请日：1991-12-30
IPC: H04J3/07
Abstract: The mapper multiplies/demultiplies 3 VC12 (Virtual Container 12) signals to TUG21 (Tributary Unit Group 21) signals after mapping the CEPT (Conference of European and Telegram) DS1 dependant signals to the VC12 signals in the synchronous transmission system. The mapper includes an HDB3 (High Density Bipolar 3) decoder (1) converting the CEPT DS1 signal to NRZ (Non-Return to Zero) signal, a C12 mapper (3) converting the NRZ signal to the C12 signal, and a VC12 mapper (4) inserting the V5 pass overhead data into the C12 signal and generating the VC12 signal by inserting the stuffing control signals (C1,C2) and stuff bits (S1,C2).
Abstract translation: 映射器将CEPT（欧洲和电报会议）DS1相关信号映射到同步传输系统中的VC12信号之后，将3 VC12（虚拟容器12）信号乘以TUG21（支路单元组21）信号。 映射器包括将CEPT DS1信号转换为NRZ（非归零）信号的HDB3（高密度双极3）解码器（1），将NRZ信号转换为C12信号的C12映射器（3）和VC12映射器 （4）将V5通过开销数据插入到C12信号中，并通过插入填充控制信号（C1，C2）和填充比特（S1，C2）来生成VC12信号。
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Patent Agency Ranking
公开(公告)号：KR1019940009768B1
公开(公告)日：1994-10-17
申请号：KR1019910023155
申请日：1991-12-17
IPC: H04J3/14
Abstract: The circuit provides an AUG signal loop interrupt monitoring circuit for monitoring AUG signal interface to form the STM-1 signal. The circuit comprises AUG MUX pass ID insertion block (1) for inserting the specific pattern in the AUG signal corresponding to 9 byte position allocated as overhead, an STM-1 MUX pass ID detector (3) for monitoring that the specific pattern is received normally, an STM-1 DEMUX pass ID insertion block (4) for receiving the STM-1 signal and processing the overhead, an AUG DEMUX pass ID detector (2) for monitoring its process and interrupting CPU.
Abstract translation: 该电路提供AUG信号环路中断监视电路，用于监视AUG信号接口，形成STM-1信号。 该电路包括用于将特定模式插入对应于作为开销分配的9字节位置的AUG信号的AUG MUX通行ID插入块（1），用于监视特定模式被正常接收的STM-1 MUX通过ID检测器（3） 用于接收STM-1信号并处理开销的STM-1 DEMUX通过ID插入块（4），用于监视其进程并中断CPU的AUG DEMUX通过ID检测器（2）。
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公开(公告)号：KR1019940009766B1
公开(公告)日：1994-10-17
申请号：KR1019910026028
申请日：1991-12-30
IPC: H04J3/00
Abstract: The system provides a pointer interpreter which is used for transferring signal in the synchronous transmission system. The system comprises a pointer status detector (1) for detecting various status of the inputted pointer a comparator (2) for comparing pointers during 2 frames, a status decision block (3) for distinguishing and concluding one of normal state, null state and NDF generation state, a control decision block (4) for producing increment or decrement control signal, an alarm generator (5) for deciding AIS and LOS status and sending alarm, negative start position generator (6) for forming clock for representing negative signal start position and reproducing negative signal.
Abstract translation: 该系统提供了用于在同步传输系统中传送信号的指针解释器。 该系统包括用于检测输入指针的各种状态的指针状态检测器（1），用于在2帧期间比较指针的比较器（2），用于区分和结束正常状态，空状态和NDF之一的状态判定块（3） 生成状态，用于产生增量或减量控制信号的控制判定块（4），用于判定AIS和LOS状态的报警发生器（5）以及发送报警负起始位置发生器（6），用于形成用于表示负信号起始位置的时钟 并再现负信号。
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公开(公告)号：KR1019940007542B1
公开(公告)日：1994-08-19
申请号：KR1019920011798
申请日：1992-07-02
IPC: H03K5/00
Abstract: The circuit is for the generation of synchronous clocks for the low and high speed subsystems. The circuit consists of a reference timing selection and observation part (1) of which input terminals are connected to the external clock, STM-1 clock and subordinate signal clock, an oscillator (12) which provides a specific reference clock to the reference timing selection and observation part, a digital phase synchronization loop (13) which produces outputs of a specific synchronous digital clock, a divider (14) for division of the digital clock, and some phase locked loops (15) for the generation of synchronous system clocks.
Abstract translation: 该电路用于为低速和高速子系统生成同步时钟。 电路由参考时序选择和观测部分（1）组成，其输入端连接到外部时钟，STM-1时钟和从属信号时钟，振荡器（12）为参考时序选择提供特定的参考时钟 和观测部分，产生特定同步数字时钟的输出的数字相位同步环路（13），用于划分数字时钟的分频器（14）和用于产生同步系统时钟的一些锁相环路（15）。
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公开(公告)号：KR1019940006724B1
公开(公告)日：1994-07-27
申请号：KR1019910026034
申请日：1991-12-30
IPC: H04J3/06
Abstract: The circuit effectively executes an alarm action according to fault states; path AIS or pointer LDSS (LOP), and performs functions of synchronous multi-system. The circuit includes a pointer state detection means (100) which has a AIS detection means (10), a NDF detection means (20), a SS detection means (30), a PV effective range detection means (40), an I/D bit inversion detection means (50), and a pointer state decision means (200) which has a NORM state decision means (60), an AIS state decision means (70) and a LOP state decision means (80), an NDF detection means (20), and a protection means to protect 1 bit error at NDF bit state detection.
Abstract translation: 电路根据故障状态有效地执行报警动作; 路径AIS或指针LDSS（LOP），并执行同步多系统的功能。 该电路包括具有AIS检测装置（10），NDF检测装置（20），SS检测装置（30），PV有效范围检测装置（40），I / D位反转检测装置（50）以及具有NORM状态判定装置（60）的指针状态判定装置（200），AIS状态判定装置（70）和LOP状态判定装置（80） 装置（20）和保护装置，用于在NDF位状态检测时保护1位错误。
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公开(公告)号：KR1019940017186A
公开(公告)日：1994-07-26
申请号：KR1019920026128
申请日：1992-12-29
IPC: H03K19/00
Abstract: 본 발명은 디지틀 동기 전송시스팀의 동기 다중화기에 적용되는 저속 다중 처리부중 DS1(1.54Mbps)신호를 VC(Virtual Cont-ainer)11에 사상하여 TU(Tributary Urit)11을 형성함에 있어 사용되는 버퍼 및 카운터들의 초기화를 위한 펄스생성기에 관한 것이다.
본 발명은 VC-11을 형성하기 위해 사용되는 시스템 클럭으로 부터 생성되는 8KHz 신호와 VC-11을 버퍼에서 읽어 나갈 한 펄스가 캡(gap)된 216K와 위상 비교를 하는 '버퍼 읽기/쓰기 위상 비교부''버퍼 쓰기용 208K신호 생성부','버퍼 읽기/쓰기 위상조절부','8K 펄스 생성부'와 '초기와 펄스 생성부'로 구성되어 있다.
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