公开(公告)号：EP2232370B1

公开(公告)日：2015-11-04

申请号：EP08856823.3

申请日：2008-12-03

Applicant: QUALCOMM Incorporated

Inventor： CODRESCU, Lucian ,  PLONDKE, Erich J. ,  VENKUMAHANTI, Suresh K

IPC: G06F9/52 ,  G06F12/10 ,  G06F9/30

CPC classification number: G06F9/526 ,  G06F9/30083 ,  G06F9/30101 ,  G06F12/1027 ,  G06F2209/522 ,  Y02D10/13

Abstract: Systems and methods including a multithreaded processor with a lock indicator are disclosed. In an embodiment, a system includes means for indicating a lock status of a shared resource in a multithreaded processor. The system includes means for automatically locking the shared resource before processing exception handling instructions associated with the shared resource. The system further includes means for unlocking the shared resource.

公开(公告)号：EP2812792A1

公开(公告)日：2014-12-17

申请号：EP13706805.2

申请日：2013-02-07

Applicant: Qualcomm Incorporated

Inventor： TABONY, Charles Joseph ,  PLONDKE, Erich James ,  CODRESCU, Lucian ,  VENKUMAHANTI, Suresh K. ,  MENEZES, Evandro Carlos

IPC: G06F9/30 ,  G06F9/32

CPC classification number: G06F9/30189 ,  G06F9/30054 ,  G06F9/30076 ,  G06F9/30149 ,  G06F9/30181 ,  G06F9/322 ,  G06F9/3816

Abstract: Systems and methods for tracking and switching between execution modes in processing systems. A processing system is configured to execute instructions in at least two instruction execution modes including a first and second execution mode chosen from a classic/aligned mode and a compressed/unaligned mode. Target addresses of selected instructions such as calls and returns are forcibly misaligned in the compressed mode, such one or more bits, such as, the least significant bits (alignment bits) of the target address in the compressed mode are different from the corresponding alignment bits in the classic mode. When the selected instructions are encountered during execution in the first mode, a decision to switch operation to the second mode is based on analyzing the alignment bits of the target address of the selected instruction.

公开(公告)号：EP2758897A2

公开(公告)日：2014-07-30

申请号：EP12784364.7

申请日：2012-09-24

Applicant: Qualcomm Incorporated

Inventor： PLONDKE, Erich J. ,  CODRESCU, Lucian ,  ZENG, Mao ,  BALASUBRAMANIAN, Swaminathan ,  HOYLE, David J.

IPC: G06F17/18 ,  G06F7/22 ,  G06F9/30 ,  G06F7/02

CPC classification number: G06F9/30021 ,  G06F7/544 ,  G06F9/30036 ,  G06F17/18

Abstract: An apparatus, system and method of determining an extremum are disclosed. A reference location identifier and a reference extremum are coupled. An input extremum of an input data set is determined and a corresponding location identifier of the input extremum is also determined. The input extremum is compared with the reference extremum to determine an output extremum and output location identifier, based on the comparison.

Abstract translation: 公开了一种确定极值的装置，系统和方法。 参考位置标识符和参考极值被耦合。 确定输入数据集的输入极值，并确定输入极值的相应位置标识符。 基于比较，将输入极值与参考极值进行比较，以确定输出极值和输出位置标识符。

公开(公告)号：EP2542963A1

公开(公告)日：2013-01-09

申请号：EP11708631.4

申请日：2011-03-02

Applicant: Qualcomm Incorporated

Inventor： CODRESCU, Lucian ,  PLONDKE, Erich James ,  INGLE, Ajay Anant ,  VENKUMAHANTI, Suresh K. ,  TABONY, Charles Joseph

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3853 ,  G06F9/30149

Abstract: A system and method of processing a hierarchical very long instruction word (VLIW) packet is disclosed. In a particular embodiment, a method of processing instructions is disclosed. The method includes receiving a hierarchical VLIW packet of instructions and decoding an instruction from the packet to determine whether the instruction is a single instruction or whether the instruction includes a subpacket that includes a plurality of sub-instructions. The method also includes, in response to determining that the instruction includes the subpacket, executing each of the sub-instructions.

公开(公告)号：EP2223225A1

公开(公告)日：2010-09-01

申请号：EP08852560.5

申请日：2008-11-19

Applicant: QUALCOMM Incorporated

Inventor： CODRESCU, Lucian ,  INGLE, Ajay, A. ,  KOOB, Christopher, E. ,  PLONDKE, Erich, J.

IPC: G06F13/16 ,  G06F12/08

CPC classification number: G06F13/161

Abstract: A system and method for selective preclusion of bus access requests are disclosed. In an embodiment, a method includes determining a bus unit access setting at a logic circuit of a processor. The method also includes selectively precluding a bus unit access request based on the bus unit access setting.

Abstract translation: 公开了一种用于选择性地排除总线访问请求的系统和方法。 在一个实施例中，一种方法包括确定在处理器的逻辑电路处的总线单元访问设置。 该方法还包括基于总线单元访问设置选择性地排除总线单元访问请求。

公开(公告)号：EP2223221A1

公开(公告)日：2010-09-01

申请号：EP08847036.4

申请日：2008-11-07

Applicant: QUALCOMM Incorporated

Inventor： BASSETT, Paul ,  CODRESCU, Lucian ,  INGLE, Ajay Anant ,  PLONDKE, Erich

IPC: G06F12/10

CPC classification number: G06F12/1027 ,  G06F2212/1028 ,  Y02D10/13

Abstract: The disclosure includes a method and system of configuring a translation lookaside buffer (TLB). In an embodiment, the TLB includes a first portion and a second portion. The first portion or the second portion may be selectively disabled in response to a value of a TLB configuration indicator.

公开(公告)号：EP2095237A2

公开(公告)日：2009-09-02

申请号：EP07854618.1

申请日：2007-11-12

Applicant: QUALCOMM Incorporated

Inventor： CODRESCU, Lucian ,  ANDERSON, William C. ,  VENKUMAHANTI, Suresh ,  GIANNINI, Louis Achille ,  PYLA, Manojkumar ,  CHEN, Xufeng

IPC: G06F11/36

CPC classification number: G06F9/3005 ,  G06F9/3009 ,  G06F9/3851 ,  G06F11/362

Abstract: A method and system provide processing instructions in a multi-threaded process including the use of breakpoint instructions for generating debugging event(s). A debugging event is generated in response to the execution of breakpoint instructions and executes debugging instructions in response to the debugging event. The debugging instructions debug processing instructions in the multi-threaded processor by transitioning at least one or more threads into a debugging mode. A debugging return is generated for reporting the executing debugging instructions in the subset of the threads of the multi-threaded processor.

公开(公告)号：EP2050003A1

公开(公告)日：2009-04-22

申请号：EP07799586.8

申请日：2007-07-13

Applicant: QUALCOMM Incorporated

Inventor： CODRESCU, Lucian ,  PLONDKE, Erich ,  AHMED, Muhammad ,  JANJANAM, Vijaya Kumar

IPC: G06F12/10

CPC classification number: G06F12/1009 ,  G06F12/1027 ,  G06F2212/684

Abstract: A method and system to indicate which page within a software-managed page table triggers an exception within a microprocessor, such as, for example, a digital signal processor, wherein a software-managed translation lookaside buffer (TLB) module receives a virtual address produced by an instruction within a Very Long Instruction Word (VLIW) packet, such as, for example, a fetch instruction, and further compares the virtual address to each stored TLB entry. If a match exists, then the TLB module outputs a corresponding mapped physical address for the instruction. Otherwise, if the VLIW packet spans two pages, where a first page is present as a TLB entry within the TLB module and the second page is missing from the stored TLB entries, an indication bit within a data field of a control register is set to identify the TLB miss exception to a software management unit. The software management unit retrieves the indication bit information from the register and further performs a page table look-up within the software-managed page table using the indication bit information in order to retrieve the missing page information. Subsequently, the missing page information is written into a new TLB entry within the TLB module for subsequent virtual address translation and execution of the packet of instructions.

公开(公告)号：EP1997229A2

公开(公告)日：2008-12-03

申请号：EP07759275.6

申请日：2007-03-23

Applicant: QUALCOMM Incorporated

Inventor： ZENG, Mao ,  CODRESCU, Lucian

IPC: H03M13/41

CPC classification number: H03M13/4107 ,  H03M13/41 ,  H03M13/4169 ,  H03M13/6505

Abstract: A Viterbi pack instruction is disclosed that masks the contents of a first predicate register with a first masking value and masks the contents of a second predicate register with a second masking value. The resulting masked data is written to a destination register. The Viterbi pack instruction may be implemented in hardware, firmware, software, or any combination thereof.

公开(公告)号：EP3149947B1

公开(公告)日：2020-07-22

申请号：EP15724831.1

申请日：2015-04-30

Applicant: Qualcomm Incorporated

Inventor： ZHOU, Bo ,  ZENG, Mao ,  PLONDKE, Erich James ,  CODRESCU, Lucian ,  XIAO, Shu ,  DU, Junchen ,  JALIL, Suhail

IPC: G06F9/30 ,  H04N19/91 ,  H04N19/42