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    LOW LEAKAGE DUAL STI INTEGRATED CIRCUIT INCLUDING FDSOI TRANSISTORS
    122.
    发明申请
    LOW LEAKAGE DUAL STI INTEGRATED CIRCUIT INCLUDING FDSOI TRANSISTORS 审中-公开
    低漏电双集成电路，包括FDSOI晶体管

    公开(公告)号：WO2014131459A1

    公开(公告)日：2014-09-04

    申请号：PCT/EP2013/054081

    申请日：2013-02-28

    Applicant: COMMISSARIAT À L'ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES ,  INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMICROELECTRONICS, INC.

    Inventor： VINET, Maud ,  CHENG, Kangguo ,  DORIS, Bruce ,  GRENOUILLET, Laurent ,  KHAKIFIROOZ, Ali ,  LE TIEC, Yannick ,  LIU, Qing

    IPC: H01L27/12 ,  H01L21/762 ,  H01L21/8238

    CPC classification number: H01L27/1203 ,  H01L21/2236 ,  H01L21/26513 ,  H01L21/76229 ,  H01L21/76237 ,  H01L21/823878 ,  H01L21/823892 ,  H01L21/84 ,  H01L27/0928 ,  H01L29/0649

    Abstract: The invention relates to an integrated circuit (9), including: -a UTBOX layer (4); -a first cell, comprising: -FDSOI transistors (1a, 1b); -a first STI (23) separating said transistors; -a first ground plane (31) located beneath one of said transistors and beneath said UTBOX layer (4); -a first well (93); -a second cell, comprising : -FDSOI transistors (1c, 1d); -a second STI (25) separating said transistors; -a second ground plane (32) located beneath one of said transistors and beneath said UTBOX layer (4); -a second well (94); -a third STI (24) separating said cells, reaching the bottom of said first and second wells (93, 94); -a deep well (92) extending continuously beneath said first and second wells, having a portion (33) beneath said third STI (24) whose doping density is at least 50% higher than the doping density of the deep well beneath said first and second STIs.

    Abstract translation: 本发明涉及一种集成电路（9），包括： - 一个UTBOX层（4）; - 第一电池，包括：-FDSOI晶体管（1a，1b）; - 分离所述晶体管的第一STI（23） - 位于所述晶体管中的一个之下并位于所述UTBOX层（4）下方的第一接地平面（31）。 - 第一口井（93）; - 第二电池，包括：-FDSOI晶体管（1c，1d）; - 分离所述晶体管的第二STI（25） - 位于所述晶体管中的一个之下并位于所述UTBOX层（4）下方的第二接地平面（32）; 第二口（94）; - 分离所述细胞的第三STI（24），到达所述第一和第二孔（93,94）的底部; - 深井（92），其在所述第一和第二井下方连续延伸，具有在所述第三STI（24）下方的部分（33），所述第三STI（24）的掺杂密度比所述第一和第二阱下面的深井的掺杂密度高至少50％ 第二STIs。

    METHOD FOR FABRICATING MICROELECTRONIC DEVICES WITH ISOLATION TRENCHES PARTIALLY FORMED UNDER ACTIVE REGIONS
    123.
    发明申请
    METHOD FOR FABRICATING MICROELECTRONIC DEVICES WITH ISOLATION TRENCHES PARTIALLY FORMED UNDER ACTIVE REGIONS 审中-公开
    用于在有源区域部分地形成隔离斜面的微电子器件制造方法

    公开(公告)号：WO2014039034A1

    公开(公告)日：2014-03-13

    申请号：PCT/US2012/053768

    申请日：2012-09-05

    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  STMICROELECTRONICS, INC. ,  GRENOUILLET, Laurent ,  LE TIEC, Yannick ,  LOUBET, Nicolas ,  VINET, Maud ,  WACQUEZ, Romain

    Inventor： GRENOUILLET, Laurent ,  LE TIEC, Yannick ,  LOUBET, Nicolas ,  VINET, Maud ,  WACQUEZ, Romain

    IPC: H01L31/0376

    CPC classification number: H01L21/76283 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3086 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/84

    Abstract: A method of producing a microelectronic device in a substrate comprising a first semiconductor layer, a dielectric layer and a second semiconductor layer, comprising the following steps : etching a trench through the first semiconductor layer, the dielectric layer and a part of the thickness of the second semiconductor layer, thus defining, in the first semiconductor layer, one active region of the microelectronic device, ionic implantation in one or more side walls of the trench, at the level of the second semiconductor layer, modifying the crystallographic properties and/or the chemical properties of the implanted semiconductor, etching of the implanted semiconductor such that at least a part of the trench extends under a part of the active region, - filling of the trench with a dielectric material, forming an isolation trench surrounding the active region and comprising portions extending under a part of the active region.

    Abstract translation: 一种在包括第一半导体层，电介质层和第二半导体层的衬底中制造微电子器件的方法，包括以下步骤：通过所述第一半导体层，所述电介质层和所述第一半导体层的厚度的一部分蚀刻沟槽 从而在所述第一半导体层中限定所述微电子器件的一个有源区域，在所述沟槽的一个或多个侧壁中的离子注入，在所述第二半导体层的水平处，修改所述晶体学性质和/或所述第二半导体层， 注入半导体的化学性质，蚀刻注入的半导体，使得沟槽的至少一部分在有源区的一部分下延伸; - 用介电材料填充沟槽，形成围绕有源区的隔离沟槽，并且包括 在有源区域的一部分下延伸的部分。

    TRANSISTOR WITH COUNTER-ELECTRODE CONNECTION AMALGAMATED WITH THE SOURCE/DRAIN CONTACT
    124.
    发明申请
    TRANSISTOR WITH COUNTER-ELECTRODE CONNECTION AMALGAMATED WITH THE SOURCE/DRAIN CONTACT 审中-公开
    带有与电源/漏液接触的反电极连接的晶体管

    公开(公告)号：WO2012015393A1

    公开(公告)日：2012-02-02

    申请号：PCT/US2010/043337

    申请日：2010-07-27

    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  STMICROELECTRONICS, INC. ,  VINET, Maud ,  LIU, Qing

    Inventor： VINET, Maud ,  LIU, Qing

    IPC: H01L21/336 ,  H01L21/74 ,  H01L29/786

    CPC classification number: H01L29/78 ,  H01L21/743 ,  H01L21/76895 ,  H01L21/823418 ,  H01L21/823475 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/84 ,  H01L29/41733 ,  H01L29/66477 ,  H01L29/66772 ,  H01L29/78645 ,  H01L29/78648

    Abstract: Transistor with counter-electrode connection amalgamated with the source/drain contact The field effect device (7) comprises an active area (5) made from semi-conducting material (4) and a gate electrode (8) separated from the active area (5) by a dielectric gate material (9). A counter-electrode (14) is separated from the active area (5) by a layer (3) of electrically insulating material. Two source/drain contacts (12, 13) are arranged on the active area (5) on each side of the gate electrode (8). One of the source/drain contacts (13) is made from a single material, overspills from the active area (5) and connects the active area (5) with the counter-electrode (14). The counter-electrode contact (13) is delineated by a closed peripheral insulating pattern (6).

    Abstract translation: 具有与源极/漏极接触连接的对电极连接的晶体管场效应器件（7）包括由半导电材料（4）制成的有源区域（5）和与有源区域（5）分离的栅电极（8） ）通过介质栅极材料（9）。 反电极（14）通过电绝缘材料层（3）与有源区域（5）分离。 在栅电极（8）的每一侧上的有源区（5）上布置有两个源极/漏极触点（12,13）。 源极/漏极触点（13）中的一个由单个材料制成，从有源区域（5）突出并且将有源区域（5）与对电极（14）连接。 对电极触点（13）由封闭的外围绝缘图案（6）描绘。

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