公开(公告)号：US20240272004A1

公开(公告)日：2024-08-15

申请号：US18108154

申请日：2023-02-10

Applicant: STMicroelectronics International N.V.

Inventor： Enri DUQI ,  Giorgio ALLEGATO

IPC: G01J5/10 ,  B81B7/00 ,  B81C1/00

CPC classification number: G01J5/10 ,  B81B7/0038 ,  B81B7/007 ,  B81C1/00285 ,  B81C1/00301 ,  B81B2201/0278 ,  B81B2207/012 ,  B81B2207/07 ,  B81B2207/097 ,  B81C2203/0109 ,  B81C2203/0792 ,  G01J2005/106

Abstract: Disclosed herein is a method of forming a thermal sensor, including patterning an active layer on a first face of a handle substrate to form a frame, a mass carrying at least one thermally isolated MOS (TMOS) transistor, and a spring structure connecting the mass to the frame while thermally isolating the mass from the frame. The frame is then bonded to pads on a first face of an integrated circuit substrate. The handle substrate is removed, and a top cap is bonded to the first face of the integrated circuit substrate to enclose at least the mass and spring within the sealed cavity.

公开(公告)号：US20240266425A1

公开(公告)日：2024-08-08

申请号：US18422867

申请日：2024-01-25

Applicant: STMicroelectronics International N.V.

Inventor： Aurore CONSTANT ,  Ferdinando IUCOLANO ,  Cristina TRINGALI ,  Maria Eloisa CASTAGNA

IPC: H01L29/778 ,  H01L29/66

CPC classification number: H01L29/778 ,  H01L29/66462

Abstract: The present disclosure relates to a method of forming an HEMT transistor, comprising the following successive steps: a) providing a stack comprising a semiconductor channel layer, a semiconductor barrier layer on top of and in contact with the semiconductor channel layer, and a semiconductor gate layer arranged on top of and in contact with the semiconductor barrier layer, the semiconductor gate layer comprising P-type dopant elements; and b) compensating for the P-type doping with oxygen atoms, in an upper portion of the semiconductor gate layer, by an oxygen anneal, so as to define a PN junction at the interface between the upper portion and a central portion of the semiconductor gate layer.

公开(公告)号：US20240266343A1

公开(公告)日：2024-08-08

申请号：US18418051

申请日：2024-01-19

Applicant: STMicroelectronics International N.V.

Inventor： Anuj BHARDWAJ ,  Anand Kumar MISHRA ,  Rohit Kumar GUPTA

IPC: H01L27/02 ,  H01L21/762 ,  H01L23/538 ,  H01L29/06

CPC classification number: H01L27/0207 ,  H01L21/76224 ,  H01L23/5386 ,  H01L29/0607

Abstract: An integrated circuit includes a semiconductor substrate patterned to include a first semiconductor track and a second semiconductor track separated from each other by a trench isolation region. The integrated circuit includes a logic circuit including a transistor having a first drain subregion in the first semiconductor track, a second drain subregion in the second semiconductor track, a first source subregion in the first semiconductor track, and a second source subregion in the second semiconductor track. A diffusion bridge of semiconductor material extends between the first and second semiconductor tracks and connects the first source subregion to the second source subregion. The first drain subregion and the second drain subregion are electrically connected by a drain metalization.

公开(公告)号：US20240265940A1

公开(公告)日：2024-08-08

申请号：US18417588

申请日：2024-01-19

Applicant: STMicroelectronics International N.V.

Inventor： Michele Boscolo Berto ,  Ezio Galbiati

IPC: G11B5/55 ,  G11B19/20 ,  H02P7/025

CPC classification number: G11B5/5569 ,  G11B19/2009 ,  H02P7/025

Abstract: Embodiments provide a method of operating a voice coil motor via a transconductance loop. The method includes detecting an actual value of a supply voltage of the transconductance loop. An offset compensation signal of the transconductance loop is produced as a function of the detected actual value of the supply voltage based on a relationship between offset values and the supply voltage of the transconductance loop. The offset compensation signal is applied to a loop control signal of the transconductance loop. A drive current is applied to the voice coil motor. The drive current is related to a target drive current that is based on the loop control signal.

公开(公告)号：US20240265249A1

公开(公告)日：2024-08-08

申请号：US18105729

申请日：2023-02-03

Applicant: STMicroelectronics International N.V.

Inventor： Danilo Pietro Pau ,  Prem Kumar Ambrose

IPC: G06N3/08

CPC classification number: G06N3/08

Abstract: Methods, apparatuses, systems, and computer program products for artificial intelligence and machine learning for resource constrained devices and systems, including for classifier learning from a stream of data. A classifier may include a neural network comprised of a plurality of layers with each layer comprised of a plurality of neurons. The neural network may include a hidden layer comprised of a plurality of hidden neurons. In various embodiments, the size of the hidden layer may be constrained and the training of a hidden layer included removing one or more hidden neurons from the hidden layer.

公开(公告)号：US12046324B2

公开(公告)日：2024-07-23

申请号：US17861458

申请日：2022-07-11

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics (Crolles 2) SAS

Inventor： Harsh Rawat ,  Praveen Kumar Verma ,  Promod Kumar ,  Christophe Lecocq

IPC: G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C8/08 ,  G11C8/10 ,  G11C11/00

CPC classification number: G11C8/10 ,  G11C7/1087 ,  G11C7/222 ,  G11C8/08

Abstract: A memory circuit includes an array of memory cells arranged with first word lines connected to a first sub-array storing less significant bits of data and second word lines connected to a second sub-array storing more significant bits of data. A row decoder circuit coupled to the first and second word lines generates word line signals. A word line gating circuit is configured to selectively gate passage of the word line signals to the second word lines for the second sub-array in response to assertion of a maximum value signal. A data modification circuit performs a mathematical operation on data read from the array of memory cells, and asserts the maximum value signal if the mathematical operation performed on the less significant bits of data from the first sub-array produces a maximum data value.

公开(公告)号：US20240243945A1

公开(公告)日：2024-07-18

申请号：US18155094

申请日：2023-01-17

Applicant: STMicroelectronics International N.V.

Inventor： Avneep Kumar GOYAL ,  Nicolas GUION ,  Sumit Kumar SINGHAL ,  Jagtar SINGH ,  Dhulipalla Phaneendra KUMAR

IPC: H04L12/40

CPC classification number: H04L12/40143 ,  H04L2012/40215

Abstract: Apparatuses and computer-implemented methods for implementing a message-based protocol interface with a communication bus are provided. An example apparatus for implementing a message-based protocol interface with a communication bus may include message handler core circuitry having a transmit message buffer, wherein the transmit message buffer is configured to store a portion of a transmit message. The apparatus may further include receive handler circuitry configured to store a portion of a received message. The apparatus further includes a message handler processor comprising a processor and an instruction memory including program code, the instruction memory and program code configured to, with the processor, cause the message handler processor to transmit at least the portion of the transmit message from a transmit data memory to the message handler core circuitry and receive the received message from the receive handler circuitry into a receive data memory.

公开(公告)号：US20240243698A1

公开(公告)日：2024-07-18

申请号：US18409527

申请日：2024-01-10

Applicant: STMicroelectronics International N.V.

Inventor： Nunzio SPINA ,  Alessandro CASTORINA ,  Giuseppe PALMISANO

IPC: H03F1/02 ,  H03F3/45 ,  H03K5/24

CPC classification number: H03F1/0233 ,  H03F3/45475 ,  H03K5/24 ,  H03F2200/105

Abstract: An envelope detector receives a modulated signal and a differential stage coupled to the detector produces a replica modulated signal compared to produce a PWM-modulated signal having on and off times. A first switch is actuated to short-circuit the input to the envelope detector. A second switch is actuated to feed back to a storage capacitor a signal indicative of the difference between inputs to the differential stage. A third switch is actuated to short-circuit an input to the comparator. Logic circuitry activates the switched to implement offset compensation where: the first, second and third switches are actuated in the absence of the PWM-modulated signal during start-up and standby phases; and the first, second and third switches are actuated during off times of the PWM-modulated signal in a working phase alternating with the start-up/standby phases.

公开(公告)号：US12032747B1

公开(公告)日：2024-07-09

申请号：US18167500

申请日：2023-02-10

Applicant: STMicroelectronics International N.V.

Inventor： Stefano Paolo Rivolta ,  Roberto Mura ,  Edoardo Nagali

IPC: G06F3/01 ,  G01V8/00

CPC classification number: G06F3/017 ,  G01V8/005

Abstract: The present disclosure is directed to devices and methods for detecting dimming gestures using infrared detection. Infrared signals are detected using a thermal metal-oxide-semiconductor (TMOS) infrared (IR) sensor solution. The TMOS IR sensor is highly accurate and has low power consumptions compared to traditional IR sensors that utilize IR receivers.

公开(公告)号：US20240213153A1

公开(公告)日：2024-06-27

申请号：US18541497

申请日：2023-12-15

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics International N.V. ,  STMicroelectronics France

Inventor： Olivier Weber ,  Rohit Kumar Gupta ,  Eric Vandenbossche

IPC: H01L27/092 ,  H01L23/528 ,  H01L27/02

CPC classification number: H01L27/0928 ,  H01L23/528 ,  H01L27/0207

Abstract: An electronic device including a first active area of a first transistor, a first insulating region forming a first insulation of the first active area, a first insulating gate extending above the first active area and forming a second insulation of the first active area, and a first insulating gate contact coupled to the first insulating gate and positioned above both the first active area and the first insulating region, wherein the first insulating gate contact couples the first insulating gate to a power supply rail.