公开(公告)号：WO2006126092A3

公开(公告)日：2007-04-26

申请号：PCT/IB2006001468

申请日：2006-05-26

Applicant: ATI TECHNOLOGIES INC ,  ATI INT SRL ,  CAMPBELL JON ,  RIBBLE MAURICE

Inventor： CAMPBELL JON ,  RIBBLE MAURICE

IPC: G06T1/20 ,  G06T15/00

CPC classification number: G06F15/16 ,  G06T1/20 ,  G06T15/005

Abstract: Systems and methods are provided for processing data. The systems and methods include multiple processors that each couple to receive commands and data, where the commands and/or data correspond to frames of video that include multiple pixels. An interlink module is coupled to receive processed data corresponding to the frames from each of the processors. The interlink module divides a first frame into multiple frame portions by dividing pixels of the first frame using at least one balance point. The interlink module dynamically determines a position for the balance point that minimizes differences between the workload of the processors during processing of commands and/or data of one or more subsequent frames.

Abstract translation: 提供了处理数据的系统和方法。 系统和方法包括每个耦合以接收命令和数据的多个处理器，其中命令和/或数据对应于包括多个像素的视频帧。 互连模块被耦合以接收对应于来自每个处理器的帧的处理数据。 互连模块通过使用至少一个平衡点划分第一帧的像素来将第一帧划分成多个帧部分。 互连模块动态地确定在处理命令和/或一个或多个后续帧的数据期间最小化处理器的工作量之间的平衡点的位置。

公开(公告)号：WO2007038732A1

公开(公告)日：2007-04-05

申请号：PCT/US2006/038005

申请日：2006-09-27

Applicant: ATI TECHNOLOGIES, INC. ,  BRENNAN, Christopher

Inventor： BRENNAN, Christopher

IPC: G06T15/50

CPC classification number: G06T15/503 ,  G06T11/40

Abstract: Described are a graphics processing unit (GPU) and a sample-level screen-door transparency technique for rendering transparent objects. The GPU includes a scan converter and a shader. The scan converter identifies pixels to be processed for rendering a transparent object and divides each pixel into a plurality of samples. The shader generates, for one of the identified pixels, an application developer-specified transparency sample mask indicating which samples of the pixel are to be suppressed when determining a color of the pixel. Execution of an application developer-specified sample mask command produces a pattern of bits that map to samples of the pixel. The values of the bits determine which samples of the pixel may be used and which samples are to be suppressed when determining a color of the pixel.

Abstract translation: 描述了用于渲染透明对象的图形处理单元（GPU）和样本级屏幕门透明度技术。 GPU包括扫描转换器和着色器。 扫描转换器识别要处理的像素以呈现透明对象，并将每个像素划分成多个样本。 着色器为所识别的像素之一生成应用程序开发者指定的透明度采样掩码，指示在确定像素的颜色时要抑制像素的哪些样本。 执行应用程序开发人员指定的样本掩码命令会产生映射到像素样本的位图。 当确定像素的颜色时，这些位的值确定可以使用像素的哪些采样以及要抑制的样本。

公开(公告)号：WO2007036800A2

公开(公告)日：2007-04-05

申请号：PCT/IB2006002766

申请日：2006-09-28

Applicant: ATI TECHNOLOGIES INC ,  ATI INT SRL ,  ALEKSIC MILIVOJE ,  GOMA SERGIU

Inventor： ALEKSIC MILIVOJE ,  GOMA SERGIU

IPC: H03M13/00 ,  H04L1/00

CPC classification number: H04L1/0057 ,  H03M13/19 ,  H03M13/27 ,  H04L1/0083

Abstract: To derive a Hamming code to manage data errors a set of at least four parity bit positions is selected for parity bits which will protect a set of data bits (where each data bit has a data bit position in the data bit set). A syndrome is determined for each data bit position. This involves selecting a unique sub-set of at least three parity bit positions. The unique sub-set shares at least one parity bit position with at least one other unique sub-set of at least three parity bit positions. A parity bit value may then be calculated for each parity bit position based on the determined syndromes. The header of a packet may be provided with a word which defines the length of the packet and an error management code generated utilizing this word so that errors in the word may be detected and, possibly, corrected.

Abstract translation: 为了导出汉明码以管理数据错误，为奇偶校验位选择至少四个奇偶校验位位置的集合，这将保护一组数据位（其中每个数据位在数据位集合中具有数据位位置）。 针对每个数据位位置确定综合征。 这包括选择至少三个奇偶校验位位置的唯一子集。 唯一子集与至少三个奇偶校验位位置的至少一个其他唯一子集共享至少一个奇偶校验位位置。 然后可基于所确定的校验子为每个奇偶校验位位置计算奇偶校验位值。 分组的报头可以提供有定义分组长度的字和利用该字生成的错误管理码，以便可以检测并且可能校正该字中的错误。

公开(公告)号：WO2006097846A3

公开(公告)日：2006-09-21

申请号：PCT/IB2006/000784

申请日：2006-03-17

Applicant: ATI TECHNOLOGIES, INC. ,  ATI INTENATIONAL SRL ,  GLEN, David, I., J.

Inventor： GLEN, David, I., J.

IPC: G09G5/391 ,  G09G5/395

Abstract: An image processing circuit, such as a graphics accelerator chip or any other suitable circuit, includes display output control logic that is operative to receive a current frame of information from a frame buffer and is operative to process a current frame, such as by providing gamma correction, image scaling, graphics or video overlaying, or other suitable processing, to produce a processed current display frame and stores the processed current display frame back in the frame buffer. Fixed function or dedicated, display type specific temporal processing logic receives the processed current display frame stored in the frame buffer and also obtains at least one previous processed current display frame from the frame buffer and temporally processes pixels from each of the processed current display frame and the previous processed current display frame to produce a temporally compensated display frame for a specific type of display.

公开(公告)号：WO2006097846A2

公开(公告)日：2006-09-21

申请号：PCT/IB2006000784

申请日：2006-03-17

Applicant: ATI TECHNOLOGIES INC ,  ATI INTENAT SRL ,  GLEN DAVID I J

Inventor： GLEN DAVID I J

IPC: G09G5/391 ,  G09G5/395

CPC classification number: G09G5/395 ,  G09G2320/0252 ,  G09G2340/16

Abstract: An image processing circuit, such as a graphics accelerator chip or any other suitable circuit, includes display output control logic that is operative to receive a current frame of information from a frame buffer and is operative to process a current frame, such as by providing gamma correction, image scaling, graphics or video overlaying, or other suitable processing, to produce a processed current display frame and stores the processed current display frame back in the frame buffer. Fixed function or dedicated, display type specific temporal processing logic receives the processed current display frame stored in the frame buffer and also obtains at least one previous processed current display frame from the frame buffer and temporally processes pixels from each of the processed current display frame and the previous processed current display frame to produce a temporally compensated display frame for a specific type of display.

Abstract translation: 诸如图形加速器芯片或任何其它合适电路的图像处理电路包括显示输出控制逻辑，其可操作以从帧缓冲器接收当前信息帧，并且可操作以处理当前帧，例如通过提供伽马 校正，图像缩放，图形或视频叠加或其他合适的处理，以产生经处理的当前显示帧并将经处理的当前显示帧存储回帧缓冲器。 固定功能或专用的显示类型特定的时间处理逻辑接收存储在帧缓冲器中的已处理的当前显示帧，并且还从帧缓冲器获取至少一个先前处理的当前显示帧，并且暂时处理来自处理过的当前显示帧和 先前处理的当前显示帧以产生用于特定类型的显示器的时间补偿的显示帧。

公开(公告)号：WO2006053320A2

公开(公告)日：2006-05-18

申请号：PCT/US2005/041324

申请日：2005-11-14

Applicant: ATI TECHNOLOGIES, INC. ,  BROWN, Andrew, S.

Inventor： BROWN, Andrew, S.

IPC: G06F1/04

CPC classification number: G06F1/04 ,  G06F1/08 ,  G11C17/143 ,  G11C17/165 ,  G11C17/18 ,  G11C29/785 ,  G11C2029/4402

Abstract: A system and method for configuring an integrated circuit. Embodiments include a method for manufacturing an integrated circuit (IC), comprising associating configuration items of the integrated circuit with at least one fuse of at least one type of fuse, wherein a fuse comprises a bit field and a physical fuse, and configuring the integrated circuit by setting the at least one fuse to a value, comprising logically combining multiple fuse values to determine a particular configuration, wherein at least one of fuse values if not alterable after manufacture of the IC.

Abstract translation: 一种用于配置集成电路的系统和方法。 实施例包括用于制造集成电路（IC）的方法，包括将集成电路的配置项与至少一种类型的熔丝的至少一个熔丝相关联，其中熔丝包括位域和物理熔丝，并且将集成电路 通过将所述至少一个熔丝设置为值，包括逻辑地组合多个熔丝值以确定特定配置，其中，在所述IC制造之后不可更改的熔丝值中的至少一个。

公开(公告)号：WO2005085977A3

公开(公告)日：2005-09-15

申请号：PCT/IB2005/000566

申请日：2005-03-02

Applicant: ATI TECHNOLOGIES, INC ,  ATI INTERNATIONAL, SRL ,  KHODORKOVSKY, Oleksandr

Inventor： KHODORKOVSKY, Oleksandr

IPC: G06F1/04

Abstract: A variable clock control information generator receives graphics engine activity data relating to the operating level of a graphics engine, and memory activity data relating to an activity level of memory. In response, the variable clock control information generator produces graphics engine clock control information and memory clock control information with respect to each other, such that a relative difference between the graphics engine activity data and the memory activity data is within balance threshold data. Accordingly, the variable clock control information generator adapts to the varying levels of graphics engine activity and memory activity and adjusts the frequency of the graphics engine clock signal and the frequency of the memory clock signal to achieve a balanced relative activity level.

公开(公告)号：WO2005085977A2

公开(公告)日：2005-09-15

申请号：PCT/IB2005000566

申请日：2005-03-02

Applicant: ATI TECHNOLOGIES INC ,  ATI INT SRL ,  KHODORKOVSKY OLEKSANDR

Inventor： KHODORKOVSKY OLEKSANDR

IPC: G06F1/04 ,  G06F1/32 ,  G09G5/18

CPC classification number: G09G5/18 ,  G06F1/3218 ,  G06F1/3225 ,  G06F1/324 ,  G06F1/3265 ,  G06F1/3275 ,  G09G2330/021 ,  Y02D10/126 ,  Y02D10/14 ,  Y02D10/153

Abstract: A variable clock control information generator receives graphics engine activity data relating to the operating level of a graphics engine, and memory activity data relating to an activity level of memory. In response, the variable clock control information generator produces graphics engine clock control information and memory clock control information with respect to each other, such that a relative difference between the graphics engine activity data and the memory activity data is within balance threshold data. Accordingly, the variable clock control information generator adapts to the varying levels of graphics engine activity and memory activity and adjusts the frequency of the graphics engine clock signal and the frequency of the memory clock signal to achieve a balanced relative activity level.

Abstract translation: 可变时钟控制信息生成器接收与图形引擎的操作级别相关的图形引擎活动数据，以及与存储器的活动级别相关的存储器活动数据。 作为响应，可变时钟控制信息发生器相对于彼此产生图形引擎时钟控制信息和存储器时钟控制信息，使得图形引擎活动数据和存储器活动数据之间的相对差异在平衡阈值数据内。 因此，可变时钟控制信息发生器适应图形引擎活动和存储器活动的变化水平，并且调整图形引擎时钟信号的频率和存储器时钟信号的频率以实现平衡的相对活动水平。

公开(公告)号：WO2008013741A3

公开(公告)日：2008-05-29

申请号：PCT/US2007016421

申请日：2007-07-20

Applicant: ATI TECHNOLOGIES INC ,  BLEIWEISS AVI I ,  BARON GERARD S

Inventor： BLEIWEISS AVI I ,  BARON GERARD S

IPC: G06F17/50 ,  A63F13/00 ,  G06F19/00

CPC classification number: G06F17/5009 ,  A63F13/00 ,  A63F2300/203 ,  A63F2300/64 ,  A63F2300/643

Abstract: The present invention is directed to a method, computer program product, and system for performing physics simulations on at least one graphics processor unit (GPU). The method includes the following steps. First, data representing physical attributes associated with at least one mesh are mapped into a plurality of memory arrays to set up of a linear system of equations that governs motion of the at least one mesh depicted in a scene. Then, computations are performed on the data in the plurality of memory arrays using at least one pixel processor to solve the linear system of equations for an instant of time, wherein modified data representing the solution to the linear system of equations for the instant of time are stored in the plurality of memory arrays.

Abstract translation: 本发明涉及用于对至少一个图形处理器单元（GPU）执行物理仿真的方法，计算机程序产品和系统。 该方法包括以下步骤。 首先，将表示与至少一个网格相关联的物理属性的数据映射到多个存储器阵列中，以建立控制场景中描绘的至少一个网格的运动的线性方程系统。 然后，使用至少一个像素处理器对多个存储器阵列中的数据执行计算以求解在时间瞬间的线性方程组，其中修改的数据表示对于时间瞬间的线性方程组的解决方案 被存储在多个存储器阵列中。

公开(公告)号：WO2008028013A2

公开(公告)日：2008-03-06

申请号：PCT/US2007/077191

申请日：2007-08-30

Applicant: ATI TECHNOLOGIES, INC. ,  LYASHEVSKY, Alexander ,  YANG, Jason ,  PREETHAM, Arcot, J.

Inventor： LYASHEVSKY, Alexander ,  YANG, Jason ,  PREETHAM, Arcot, J.

CPC classification number: H04N19/436 ,  H04N19/44

Abstract: Embodiments of a method and system for motion compensation in decoding video data are described herein. In various embodiments, a high-compression-ratio codec (such as H.264) is part of the encoding scheme for the video data. Embodiments pre-process control maps that were generated from encoded video data, and generating intermediate control maps comprising information regarding decoding the video data. The control maps indicate which one of multiple prediction operations is to be used in performing motion compensation on particular units of data in a frame. In an embodiment, motion compensation is performed on a frame basis such that each of the multiple prediction operations is performed on an entire frame at one time, In other embodiments, processing of different frames is interleaved. Embodiments increase the efficiency of the motion compensation such as to allow decoding of high-compression- ratio encoded video data on personal computers or comparable equipment without special, additional decoding hardware.

Abstract translation: 本文描述了用于解码视频数据中的运动补偿的方法和系统的实施例。 在各种实施例中，高压缩率编解码器（例如H.264）是视频数据的编码方案的一部分。 实施例从编码视频数据生成的预处理控制图，以及生成包括关于解码视频数据的信息的中间控制图。 控制图表示在帧中对特定的数据单元执行运动补偿时将使用多个预测操作中的哪一个。 在一个实施例中，在帧的基础上执行运动补偿，使得多次预测操作中的每一个在一次的整个帧上执行。在其他实施例中，不同帧的处理被交织。 实施例增加了运动补偿的效率，例如允许在个人计算机或类似设备上对高压缩比编码视频数据进行解码而没有特殊的附加解码硬件。