公开(公告)号：JPH02178738A

公开(公告)日：1990-07-11

申请号：JP28162589

申请日：1989-10-26

Applicant: ADVANCED MICRO DEVICES INC

Inventor： SAFUDAA MAAMOTSUDO AASUGAA ,  JIYOON GUREI BAATOKOUBIATSUKU ,  ERITSUKU AREN SASU

IPC: G06F11/00 ,  G06F11/10 ,  G06F11/14

Abstract: PURPOSE: To detect an error in arithmetic operation of two operands at high speed by adding each digit of the two operands to compare both operands for mutually adding the resultant digits to obtain a mean sum. CONSTITUTION: Resultant digits of arithmetic operation of two operands 10 and 12 are mutually added together in an adder 14, and the step of this addition is repeated until the first single digits are achieved. Further, each digit of operand 10 and that of operand 12 are added to each other to obtain a mean sum. Digits of the mean sum are mutually and sequentially added repeatedly until the second single digits are achieved. The number of the first single digits is compared with the number of the second single digits, and if the comparison fails, an error signal indicating the failure of comparison is issued. With that, an error that occurs during one clock cycle of arithmetic operation of at least two operands can be detected and corrected.

公开(公告)号：JPH02144650A

公开(公告)日：1990-06-04

申请号：JP26284589

申请日：1989-10-06

Applicant: ADVANCED MICRO DEVICES INC

Inventor： JIYOOZEFU FURANKURIN EIKINZU ,  DONARUDO GAADAMU GODAADO ,  SHINSHIA POORETSUTE GOOSHIYOUS ,  AANESUTO DEEBITSUDO HAAKE

IPC: G06F13/36 ,  G06F13/40 ,  H03K19/018 ,  H03K19/173

Abstract: PURPOSE: To easily perform communication between elements of two different kinds of digital communication channels by providing a mask-programmable integrated circuit having a logic control means which is dynamically connected to both I/O interface means and a translation means to control their operations. CONSTITUTION: A gate array 50 is provided with a mask-programmable integrated circuit having two I/O interface elements 54 and 56 which are connected to two different communication channels 10 and 12. A translation element 58 which translates an electric signal and is connected to I/O interface elements 54 and 56 is provided between gate arrays 50. The logic control means is provided also and is connected to I/O interface elements 54 and 56 and the translation element 58 to control their operations, thereby satisfying preliminarily determined communication requests between different kinds of communication channels. Thus, communication between elements of different kinds of digital communication channels is facilitated.

公开(公告)号：JPH0298728A

公开(公告)日：1990-04-11

申请号：JP20112889

申请日：1989-08-01

Applicant: ADVANCED MICRO DEVICES INC

Inventor： YAN CHII WAN ,  POORU SUKOTSUTO

IPC: G06F5/06 ,  G06F5/16 ,  G11C7/00 ,  H03M9/00

Abstract: PURPOSE: To substantially shorten a fall-through time without the need to decrease storage capacity by providing an input control means for input from respective arrays which is coupled with respective input means and use a 1st logical function and an output control means for output from the respective arrays which is coupled with respective output means and uses a 2nd logical function. CONSTITUTION: The FIFO(first-in first-out) memory 100 includes (k) ripple- through FIFO memory arrays 1011 -1011 , which each have (n) rows and (m) bits. Input to the respective FIFO memory array 101 is controlled by the input control means 102 and output is controlled by the output control means 103. Then one of the arrays is selected by the input control means 102 in each input operation in order so as to store input data in predetermined order, and the output control means 103 selects the output from one of the arrays in the predetermined order in each output operation. Consequently, the FIFO memory is obtained which has a substantially shortened fall-through time.

公开(公告)号：JPH0264994A

公开(公告)日：1990-03-05

申请号：JP11716389

申请日：1989-05-10

Applicant: ADVANCED MICRO DEVICES INC

Inventor： PATORITSUKU TEI CHIYAN ,  ROBAATO ERU YOU ,  HIROSHI YOSHIDA ,  MUUN II WAN

IPC: G06F17/30 ,  G11C15/00 ,  G11C15/04

Abstract: PURPOSE: To attain address designation by contents by detecting existence of a skip bit in a word and existence of an empty bit in a word and eliminating the word containing the detected skip bit from searching. CONSTITUTION: Word masking can be achieved by setting to high either a skip bit or/and an empty bit. And in either case, a final match line output ML' is compelled to low through a NANT gate 47 and NOR gate 48 showing non-matching state even if a matching exists. Thus, address designation is enabled by memory and contents to be searched based on the contents of the memory data rather than by the data position on the memory.

公开(公告)号：JPH0244428A

公开(公告)日：1990-02-14

申请号：JP14653789

申请日：1989-06-08

Applicant: ADVANCED MICRO DEVICES INC

Inventor： MAIKERU EE NITSUKUSU

IPC: G06F9/48 ,  G06F13/24 ,  H03K3/037

Abstract: PURPOSE: To eliminate the obtaining error of interruption signals and the instruction for two times of a single interruption state by providing a master latch, a transfer gate, a clock operation latch, and inverter, an output driver circuit and a clear circuit in an interruption status bit circuit. CONSTITUTION: This status bit circuit 10 is provided with a master flip-flop or latch 12, the transfer gate 14, the clock operation latch 16, the inverter 18 and the output driver circuit 20. The status bit circuit 10 is also provided with the inverter 22 and a clear flip-flop or latch circuit 24. Then, when interruption input signals are not generated again, a low logic level is generated in output signals by next read signals. Thus, the obtaining error of an interruption state is eliminated and any single interruption state is not instructed for two times.

公开(公告)号：JPH0235838A

公开(公告)日：1990-02-06

申请号：JP12653289

申请日：1989-05-18

Applicant: ADVANCED MICRO DEVICES INC

Inventor： JIYON FUREDORITSUKU MATSUKUURU

IPC: H04L7/00 ,  H04J3/06 ,  H04Q11/04

Abstract: PURPOSE: To compensate differences among a transmit clock of a various station of an independently clocked network by cascading one smoother which has a threshold value less than the mean number of minimum worst cases of preamble bytes and one smoother which has a threshold value larger than the mean number of maximum worst cases together. CONSTITUTION: The smoothers operate somewhere on the upstream side of an elastic buffer and the downstream side of MAC 24. When arrival bytes are idle, a low-pass smoother operates into a reduced state. When a high-pass smoother is reduced to an extension level prior to its register, bytes in the delay register are discarded and deleted effectively. When a smoother is in a reduced state and a short preamble arrives, the smoother changes into a normal state and inserts the idle bytes in the same mode with the high-pass smoother. A Tx (transmit) clock generated by an encoder decoder receiver ERX20 has any error processed by the elastic buffer.

公开(公告)号：JPH0214552A

公开(公告)日：1990-01-18

申请号：JP1386689

申请日：1989-01-23

Applicant: ADVANCED MICRO DEVICES INC

Inventor： JIEIKOBU DEII HASUKERU

IPC: H01L21/768

Abstract: PURPOSE: To obtain a metal interconnection free from forming a hole, by patterning a metal of a lower level, forming a first dielectric layer on a layer wherein the parts between contact regions are filled up with dielectric material, forming a second dielectric layer, and etching contact holes by a two-step method. CONSTITUTION: Concerning a wafer, an oxide layer 24 is formed to cover the whole surface, and the exposed regions between interconnections 14 of a first level are filled up with glass and a layer 26 is formed. Metallic parts 14 are isolated physically and electrically from one another, and the covered wafer is flattened to the level of the metallic interconnection surfaces 14a. Next, after the formation of a nitride layer 28 an oxide layer 30 of an intermediate level is formed, and etching is performed to form contact holes 10 up to the interconnections 14 of the first level of a lower layer. But in the first step the oxide layer 30 is etched and the etching stops on the nitride layer 28 of a lower layer. Following this, the nitride layer 28 is etched to the oxide 24 and the metal 14 of the lower layers. Accordingly, it becomes possible to obtain metal interconnections without digging an oxide out round.

公开(公告)号：JPH027716A

公开(公告)日：1990-01-11

申请号：JP3093289

申请日：1989-02-09

Applicant: ADVANCED MICRO DEVICES INC

Inventor： DONARUDO EMU UORUTAAZU JIYUNIA

IPC: H03K17/695 ,  H03K17/16 ,  H03K19/003 ,  H03K19/013 ,  H03K19/017 ,  H03K19/0175 ,  H03K19/0185

Abstract: PURPOSE: To reduce the generation of inductive ringing from an output node by providing the output buffer with a pull-up circuit and a pull-down circuit. CONSTITUTION: The output buffer includes a NOR logic gate 36, a NAND logic gate 40, an inverter 44, a pull-up circuit 37, and a pull-down circuit 39. The circuit 37 includes inverters 46, 48, a 1st pull-up N-channel transistor(TR) N2, a NAND logic gate 42, and a 2nd pull-up P-channel TR P2 and the circuit 39 includes inverters 50, 52, a 1st pull-down P-channel TR P3, a NOR logic gate 38, and a 2nd pull-down N-channel TR N3. A capacitive and inductive load expressed by impedance CAP and allowed to be sharply changed is connected between an output node B and ground potential. Consequently the capacitive and inductive load to be sharply changed can be driven without generation remarkable output ringing.

公开(公告)号：JPH0160951B2

公开(公告)日：1989-12-26

申请号：JP50026879

申请日：1979-01-02

Applicant: ADVANCED MICRO DEVICES INC

Inventor： AABU DARERU EMU

IPC: G11C11/34 ,  G11C11/35 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/06 ,  H01L27/108 ,  H01L29/78

公开(公告)号：JPH01239637A

公开(公告)日：1989-09-25

申请号：JP1093789

申请日：1989-01-19

Applicant: ADVANCED MICRO DEVICES INC

Inventor： JIGII BAROA

IPC: G06F9/38 ,  G06F12/08 ,  G06F15/78

Abstract: PURPOSE: To attain caching of an interlock variable by providing an integrated cache unit(ICU) as an instruction cache and an ICU as a data cache to the computer system. CONSTITUTION: An instruction in an instruction ROM 150 and an instruction cache ICU 101 is addressed by a processor 110 via an address bus 120. The extracted instruction is fed to the processor 110 via a bus 125. A data cache ICU 102 is addressed via the address bus 120. A memory bus 175 couples a main memory 190 with the ICUs 101, 102. Furthermore, an arithmetic adder 195 is coupled with the buses 120, 121 and a data transfer controller(DTC) 198 is coupled with the bus 175 and a system bus 199. Thus, the desired object is attained.