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公开(公告)号:WO2023002294A1
公开(公告)日:2023-01-26
申请号:PCT/IB2022/056324
申请日:2022-07-08
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , IBM (CHINA) INVESTMENT COMPANY LIMITED
Inventor: REEVE, John, Anthony , KLINGER, Doina, Liliana , XING, Chengxuan , SOAL, Tom
IPC: G06F9/50
Abstract: An application configuration tool and associated method for supporting deployment of an application on a server that has a set of configurations available for applications deployed on the server. The method attempts to match every configuration required by the application to a configuration available on the server. In case of multiple candidates that match, one is selected. When there is no match an error message is generated. The method is iterated to inspect each selected configuration to identify any references contained in the selected configuration that themselves need further configurations. The iteration of inspecting and the matching to follow the references is continued until all such references are exhausted either by matching or failure to match and consequent error message generation. Finally, a configuration report is output specifying the selected configurations and, to the extent that not all required configurations have been matched to available configurations, the error messages.
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132.
公开(公告)号:WO2022269399A1
公开(公告)日:2022-12-29
申请号:PCT/IB2022/055334
申请日:2022-06-08
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , IBM (CHINA) INVESTMENT COMPANY LIMITED
Inventor: KOONE, Joseph , REDDY, Smitha , TELLEZ, Gustavo, Enrique , BOWEN, Michael, Alexander , MATHENY, Adam
IPC: G06F30/398 , G06F30/394 , G06T17/20 , G06F2119/12 , G06F30/23
Abstract: Aspects of the invention include generating a set of via mesh specifications for a cell within an integrated circuit. Each via mesh specification defines one or more straps on each layer above a first layer, which includes one or more pins that form a pin terminal, to a top layer that connects the cell to a net for interconnection of the cell with one or more other cells, and also one or more vias that interconnect adjacent ones of the layers. Aspects also include verifying whether each via mesh specification is a universally routable via mesh specification guaranteeing that the cell interconnects with other cells through the net while meeting all design rules, and including only the via mesh specifications of the set of via mesh specifications that are universally routable in a library of via mesh specifications. The library is used to finalize and fabricate the integrated circuit.
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公开(公告)号:WO2022269387A1
公开(公告)日:2022-12-29
申请号:PCT/IB2022/054851
申请日:2022-05-24
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , IBM (CHINA) INVESTMENT COMPANY LIMITED
Inventor: HARRIS, Bradley, Evan , KHAN, Moazzam , HEINLEIN, James
IPC: G06K9/62 , G06N20/00 , G06N5/027 , G06N5/04 , H04L63/1425
Abstract: One or more computer processors create a binary cluster of events by bootstrapping a set of ground truths contained with a rule engine applied to a set of high-dimensional datapoints, wherein the binary cluster contains two clusters each containing a plurality of high-dimensional datapoints; determine one or more peer groups for a set of unknown high-dimensional datapoints utilizing a trained multiclass classifier, wherein the high-dimensional datapoints are assigned to one or more peer groups by the trained multiclass classifier using an incremental learning algorithm in order to reduce system resources; create an activity distribution for each unknown high-dimensional datapoint associated with a user in the set of unknown high-dimensional datapoints and each peer group; calculate a deviation percentage between the activity distribution of the user and each peer group associated with the user; and responsive to exceeding a deviation threshold, classify the user or associated high-dimensional datapoints as risky.
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公开(公告)号:WO2022264034A1
公开(公告)日:2022-12-22
申请号:PCT/IB2022/055505
申请日:2022-06-14
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM (CHINA) INVESTMENT COMPANY LTD. , IBM DEUTSCHLAND GMBH
Inventor: ALBARAKAT, Laith , BRADBURY, Jonathan , SLEGEL, Timothy , LICHTENAU, Cedric , VON BUTTLAR, Joachim
IPC: G06N20/00 , G06F9/3836 , G06N3/04
Abstract: An exception summary is provided for an invalid value detected during instruction execution. An indication that a value determined to be invalid was included in input data to a computation of one or more computations or in output data resulting from the one or more computations is obtained. The value is determined to be invalid due to one exception of a plurality of exceptions. Based on obtaining the indication that the value is determined to be invalid, a summary indicator is set. The summary indicator represents the plurality of exceptions collectively.
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公开(公告)号:WO2022264003A1
公开(公告)日:2022-12-22
申请号:PCT/IB2022/055459
申请日:2022-06-13
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM (CHINA) INVESTMENT COMPANY LTD. , IBM DEUTSCHLAND GMBH
Inventor: SLEGEL, Timothy , ALBARAKAT, Laith , BRADBURY, Jonathan , LICHTENAU, Cedric , WEISHAUPT, Simon
IPC: G06N99/00
Abstract: An instruction is executed to perform a query function. The executing includes obtaining information relating to a selected model of a processor. The information includes at least one model-dependent data attribute of the selected model of the processor. The information is placed in a selected location for use by at least one application in performing one or more functions.
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136.
公开(公告)号:WO2022263997A1
公开(公告)日:2022-12-22
申请号:PCT/IB2022/055449
申请日:2022-06-13
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM (CHINA) INVESTMENT COMPANY LTD. , IBM DEUTSCHLAND GMBH
Inventor: WEISHAUPT, Simon , SAPORITO, Anthony , SLEGEL, Timothy
IPC: G06N3/063
Abstract: Instruction processing is performed for an instruction (700). The instruction is configured to perform a plurality of functions (702), in which a function of the plurality of functions is to be performed in a plurality of processing phases (704). A processing phase is defined to store up to a select amount of data (706). The select amount of data is based on the function to be performed (708). At least one function of the plurality of functions has a different value for the select amount of data than at least one other function (710). A determination is made as to whether a store into a designated area occurred based on processing a select processing phase of a select function (712). Based on determining that the store into the designated area occurred, an interrupt is presented (714), and based on determining that the store into the designated area did not occur, instruction processing is continued (716).
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公开(公告)号:WO2022263980A1
公开(公告)日:2022-12-22
申请号:PCT/IB2022/055409
申请日:2022-06-10
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , IBM (CHINA) INVESTMENT COMPANY LIMITED
Inventor: CUI, Shimin
IPC: G06F12/02
Abstract: Pointer alignment in a computer programming to obtain information enabling a compiler to optimize program code. Equivalence classes of pointers are collected in a program using a flow-insensitive yet field-sensitive pointer analysis operation iterating through an entire program code of the program. The equivalence classes of pointers, once collected, are mapped to and recorded in an equivalence class mapping table (ECTable). A portion of the collected equivalence classes of pointers are identified, from the ECTable, as pointer candidates for a pointer alignment computation according to a code pattern analysis of each pointer candidate. The code pattern analysis is based on available alignment information, and whether the alignment information would enable a compiler to optimize pointer references of the candidate pointer. The pointer alignment computation is then performed for each identified pointer candidate to obtain the alignment information used to optimize execution of the program.
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公开(公告)号:WO2022259089A1
公开(公告)日:2022-12-15
申请号:PCT/IB2022/055104
申请日:2022-06-01
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM (CHINA) INVESTMENT COMPANY LTD. , IBM DEUTSCHLAND GMBH
Inventor: CMIELOWSKI, Lukasz , KUCHARCZYK, Szymon , HIRZEL, Martin , LĄCZAK, Dorota
Abstract: Disclosed herein is a method of training an artificial intelligence model with adjustable parameters that is trained to provide an analysis result in response to receiving an input data set comprising one or more chosen variables. The method comprises: receiving a training data set comprising multiple groups of training input data paired with a training analysis result(400), receiving a trial analysis result from the artificial intelligence model in response to inputting the multiple groups of training input data into artificial intelligence model(402), calculating an accuracy metric descriptive of a comparison between the trail analysis result and the training analysis result(404), calculating a fairness score metric by comparing the one or more chosen variables to the trial analysis result (406), calculating a combined metric from the fairness score metric and the accuracy metric(408), and modifying the adjustable parameters using a training algorithm that receives at least the combined metric(410).
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公开(公告)号:WO2022229727A1
公开(公告)日:2022-11-03
申请号:PCT/IB2022/052592
申请日:2022-03-22
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM ISRAEL SCIENCE AND TECHNOLOGY LTD. , IBM (CHINA) INVESTMENT COMPANY LTD.
Abstract: A memory controller circuit for mapping data of a convolutional neural network to a physical memory is disclosed. The memory controller circuit comprises a receiving unit to receive a selection parameter value, and a mapping unit to map pixel values of one layer of the convolutional neural network to memory words of the physical memory according to one of a plurality of mapping schemas, wherein the mapping is dependent on the value of the received selection parameter value.
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140.
公开(公告)号:WO2022200894A1
公开(公告)日:2022-09-29
申请号:PCT/IB2022/052001
申请日:2022-03-07
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , IBM (CHINA) INVESTMENT COMPANY LIMITED
Abstract: Method and system are provided for running a smaller memory-address width program in a larger memory-address width address space. The method includes: dividing a smaller memory-address width program executable code into a set of portions; reserving a first virtual storage area in a part of an address space accessed using a smaller memory-address width address, and reserving a set of second virtual storage areas in a part of the address space accessed using a larger memory-address width address to accommodate the program executable code. The method provides a relocation mechanism to relocate a processor thread by translating using a relocation factor from an address in the reserved first virtual storage area to the one of the reserved second virtual storage areas containing the executable code.
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