公开(公告)号：US20020013876A1

公开(公告)日：2002-01-31

申请号：US09859207

申请日：2001-05-16

Applicant: STMicroelectronics S.A.

Inventor： Francesco La Rosa

IPC: G06F012/00 ,  G11C005/00 ,  G11C029/00

CPC classification number: G06F11/1068 ,  G11C16/10

Abstract: An electrically erasable and programmable memory includes a memory array having memory cells connected to word lines and bit lines. The bit lines are arranged in columns. The memory also includes read circuits connected to the bit lines and programming latches connecting the bit lines to a programming line. The memory includes a device to break the conductive paths connecting the memory cells of a column to the read circuits when data has been loaded into the latches of the column, without breaking the conductive paths that connect the latches of the column to the read circuits.

Abstract translation: 电可擦除可编程存储器包括具有连接到字线和位线的存储器单元的存储器阵列。 位线排列成列。 该存储器还包括连接到位线的读取电路和将位线连接到编程线的编程锁存器。 存储器包括当数据已经被加载到列的锁存器中时断开将列的存储单元连接到读取电路的导电路径的装置，而不会破坏将列的锁存器连接到读取电路的导电路径。

公开(公告)号：US20010055220A1

公开(公告)日：2001-12-27

申请号：US09853254

申请日：2001-05-11

Applicant: STMicroelectronics S.A.

Inventor： Richard Ferrant

IPC: G11C011/24 ,  H03H011/26

CPC classification number: G11C11/4099 ,  G11C7/14

Abstract: A voltage regulation device is for a reference cell of a dynamic random access memory arranged in lines and columns and including a plurality of memory cells. The device includes at least one capacitor of a predetermined capacitance which can be discharged during memory access.

Abstract translation: 电压调节装置用于布置成行和列并且包括多个存储单元的动态随机存取存储器的参考单元。 该装置包括至少一个预定电容的电容器，其可以在存储器存取期间被放电。

公开(公告)号：US20010021958A1

公开(公告)日：2001-09-13

申请号：US09737170

申请日：2000-12-14

Applicant: STMicroelectronics S.A.

Inventor： Sebastien Zink ,  Bruno Leconte ,  Paola Cavaleri

IPC: G06F013/00 ,  G06F012/00

CPC classification number: G11C16/10 ,  G11C2216/14

Abstract: An integrated circuit memory includes a FLASH memory including a circuit for recording a word presented on its input without the possibility of recording simultaneously several words in parallel. The integrated circuit memory may include a buffer memory with a sufficient capacity to store a plurality of words, the output of which is coupled to the input of the FLASH memory. A circuit is also included for recording into the buffer memory a series of words to be recorded into the FLASH memory and recording into the FLASH memory the words first recorded into the buffer memory.

Abstract translation: 集成电路存储器包括闪存，其包括用于记录在其输入上呈现的字的电路，而不具有并行同时记录多个字的可能性。 集成电路存储器可以包括具有足够的容量来存储多个字的缓冲存储器，其输出耦合到闪速存储器的输入端。 还包括用于将要记录到FLASH存储器中的一系列字记录到缓冲存储器中并且将首先记录到缓冲存储器中的字记录到FLASH存储器中的电路。

公开(公告)号：US20010004550A1

公开(公告)日：2001-06-21

申请号：US09731090

申请日：2000-12-06

Applicant: STMicroelectronics S.A.

Inventor： Gerard Passemard

IPC: H01L021/4763 ,  H01L021/44 ,  H01L021/31 ,  H01L021/469

CPC classification number: H01L21/76832 ,  H01L21/7681 ,  H01L21/76811 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A interconnection structure of the damascene type is produced on a surface of a microelectronic device that includes at least one dielectric material layer for housing at least one interconnection and at least one interface layer on the dielectric material layer. The interface layer may include at least one SiCH layer and at least one SiOCH layer.

Abstract translation: 镶嵌型的互连结构在微电子器件的表面上产生，该微电子器件的表面包括至少一个电介质材料层，用于容纳介电材料层上的至少一个互连和至少一个界面层。 界面层可以包括至少一个SiCH层和至少一个SiOCH层。

公开(公告)号：US20180364339A1

公开(公告)日：2018-12-20

申请号：US16000512

申请日：2018-06-05

Applicant: STMicroelectronics S.A. ,  STMicrolectronics (Research & Development) Limited

Inventor： Victor Macela ,  Ed Hawkins ,  Olivier Pothier ,  Manu Alibay

IPC: G01S7/486 ,  G01S17/02 ,  G01S17/88 ,  G06F3/01 ,  G01S17/66

Abstract: A method for acquiring tracking points belonging to a trajectory of a target object in motion, includes: emitting a radiation towards the target object; receiving a reflection of the radiation from the target object in respective fields of view of each detection zone of a network of detection zones; processing the reflection by determining distances separating the target object from an origin point by measuring a time of flight of the radiation in each detection zone; determining a degree of coverage of each detection zone; and estimating, based on the distances and on the degree of coverage of each detection zone, a position of a tracking point corresponding to a position of an extremity of the target object inside a respective detection zone chosen in a direction of motion of the target object.

公开(公告)号：US09197197B2

公开(公告)日：2015-11-24

申请号：US14050203

申请日：2013-10-09

Applicant: STMicroelectronics S.A. ,  Mentor Graphics Corporation

Inventor： Anna Asquini ,  Vincent Vallet

IPC: H03L7/00 ,  H03K3/017 ,  H03K5/1252 ,  G06F1/10 ,  G06F1/12

CPC classification number: H03K3/017 ,  G06F1/10 ,  G06F1/12 ,  H03K5/1252

Abstract: A duty cycle protection circuit including a first synchronous device adapted to receive a first clock signal on an input line and to generate a first clock transition of a second clock signal in response to a first clock transition of the first clock signal; and reset circuitry coupled to the input line and adapted to generate a second clock transition of the second clock signal by resetting the first synchronous device a time delay after the first clock transition of the first clock signal.

Abstract translation: 一种占空比保护电路，包括适于在输入线路上接收第一时钟信号的第一同步装置，并且响应于第一时钟信号的第一时钟转换而产生第二时钟信号的第一时钟转变; 以及复位电路，其耦合到所述输入线并且适于通过在所述第一时钟信号的所述第一时钟转换之后复位所述第一同步器件时间延迟来产生所述第二时钟信号的第二时钟转变。

公开(公告)号：US09018078B2

公开(公告)日：2015-04-28

申请号：US13751489

申请日：2013-01-28

Applicant: STMicroelectronics S.A. ,  Commissariat à l'Énergie Atomique et aux Énergies Alternatives

Inventor： Benoit Sklenard ,  Perrine Batude

IPC: H01L21/46 ,  H01L23/58 ,  H01L21/02 ,  H01L27/06 ,  H01L27/12 ,  H01L21/822

CPC classification number: H01L23/585 ,  H01L21/02038 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for manufacturing an integrated circuit, including the steps of forming first transistors on a first semiconductor layer; depositing a first insulating layer above the first semiconductor layer and the first transistors, and leveling the first insulating layer; depositing a conductive layer above the first insulating layer, and covering the conductive layer with a second insulating layer; bonding a semiconductor wafer to the second insulating layer; thinning the semiconductor wafer to obtain a second semiconductor layer; and forming second transistors on the second semiconductor layer.

Abstract translation: 一种用于制造集成电路的方法，包括以下步骤：在第一半导体层上形成第一晶体管; 在所述第一半导体层和所述第一晶体管之上沉积第一绝缘层，以及对所述第一绝缘层进行调平; 在第一绝缘层上方沉积导电层，并用第二绝缘层覆盖导电层; 将半导体晶片接合到所述第二绝缘层; 使半导体晶片变薄以获得第二半导体层; 以及在所述第二半导体层上形成第二晶体管。

公开(公告)号：US08847275B2

公开(公告)日：2014-09-30

申请号：US13796753

申请日：2013-03-12

Applicant: STMicroelectronics S.A.

Inventor： Jean Jimenez ,  Philippe Galy ,  Boris Heitz

IPC: H01L29/417 ,  H01L29/74 ,  H01L31/111 ,  H01L29/72 ,  H01L29/73 ,  H01L23/62 ,  H01L27/02 ,  H01L29/87 ,  H01L29/747

CPC classification number: H01L27/0259 ,  H01L27/0262 ,  H01L29/7436 ,  H01L29/747 ,  H01L29/87

Abstract: The component incorporates, in topological terms, a scalable number of triac structures in a concentric annular arrangement. The component can be used with an electronic device to protect against electrostatic discharges. For example, the components can be used to protect the input/output pad, the first power supply terminal, and the second power supply terminal of an integrated circuit against electrostatic discharges.

Abstract translation: 该组件以拓扑学方式并入具有同步环形布置的可缩放数量的三端双向可控硅结构。 该组件可与电子设备一起使用，以防止静电放电。 例如，这些组件可用于保护集成电路的输入/输出焊盘，第一电源端子和第二电源端子免受静电放电。

公开(公告)号：US20140233671A1

公开(公告)日：2014-08-21

申请号：US14177371

申请日：2014-02-11

Applicant: Institut Polytechnique de Bordeaux ,  STMicroelectronics S.A.

Inventor： DIDIER BELOT ,  Yann Deval ,  Francois Rivet

IPC: H04B1/00

CPC classification number: H04B1/0014 ,  H04B1/406 ,  H04B2001/0491

Abstract: A device for generating a signal, including: a balun; and a circuit capable of summing up, on a first access terminal of the balun, currents representative of signals received on first input terminals of the device, and on a second access terminal of the balun, currents representative of signals received on second input terminals of the device.

Abstract translation: 一种用于产生信号的装置，包括：平衡 - 不平衡转换器; 以及能够在所述平衡 - 不平衡变换器的第一接入终端上总和的电流，代表在所述设备的第一输入端子上接收的信号的电流，以及在所述平衡 - 不平衡变换器的第二接入终端上的总和的电流， 装置。

公开(公告)号：US20140217541A1

公开(公告)日：2014-08-07

申请号：US14247084

申请日：2014-04-07

Applicant: STMicroelectronics S.A. ,  STMicroelectronics (Crolles 2) SAS

Inventor： Michel Marty ,  François Roy ,  Jens Prima

IPC: H01L27/146

CPC classification number: H01L27/1464 ,  H01L27/1463 ,  H01L27/14683 ,  H01L27/14687 ,  H01L27/14689

Abstract: A method for forming a back-side illuminated image sensor, including the steps of: a) forming, from the front surface, doped polysilicon regions, of a conductivity type opposite to that of the substrate, extending in depth orthogonally to the front surface and emerging into the first layer; b) thinning the substrate from its rear surface to reach the polysilicon regions, while keeping a strip of the first layer; c) depositing, on the rear surface of the thinned substrate, a doped amorphous silicon layer, of a conductivity type opposite to that of the substrate; and d) annealing at a temperature capable of transforming the amorphous silicon layer into a crystallized layer.

Abstract translation: 一种用于形成背面照明图像传感器的方法，包括以下步骤：a）从前表面形成与衬底相反的导电类型的掺杂多晶硅区域，其垂直于正面延伸， 进入第一层; b）使衬底从其后表面变薄到达多晶硅区域，同时保持第一层的条带; c）在所述薄化衬底的后表面上沉积与所述衬底相反的导电类型的掺杂非晶硅层; 和d）在能够将非晶硅层转变成结晶层的温度下退火。