公开(公告)号：US20180239384A1

公开(公告)日：2018-08-23

申请号：US15693214

申请日：2017-08-31

Applicant: STMicroelectronics (Alps) SAS ,  STMicroelectronics (Grenoble 2) SAS

Inventor： Serge Ramet ,  Sandrine Nicolas ,  Danika Perrin ,  Cedric Rechatin

IPC: G05F3/26 ,  H03F3/195

CPC classification number: G05F3/262 ,  G05F1/46 ,  H03F3/16 ,  H03F3/195 ,  H03F2200/294

Abstract: An integrated circuit includes a first stage configured to receive a bias current. A current regulation loop includes a transimpedance amplifier having a first transistor, and a second transistor having a gate coupled to a gate of the first transistor. The first transistor and the second transistor are configured to compare the bias current with a reference current, and to generate a regulation voltage on an output node of the transimpedance amplifier. A capacitor is coupled between the output node of the transimpedance amplifier and the gates of the first and second transistors.

公开(公告)号：US09933797B1

公开(公告)日：2018-04-03

申请号：US15495504

申请日：2017-04-24

Applicant: STMicroelectronics (Alps) SAS

Inventor： Frederic Lebon

IPC: G05F3/22 ,  G05F1/46 ,  G05F3/30

CPC classification number: G05F1/468 ,  G05F3/30

Abstract: An integrated electronic device includes a core having a first terminal and a second terminal. The core includes a first branch with a first diode-connected bipolar transistor coupled in series to a first resistor between the first terminal and a reference terminal intended to be supplied with a reference voltage, and a second branch with a second diode-connected bipolar transistor coupled between the second terminal and the reference terminal. The second diode-connected bipolar transistor has a current density higher than the first diode-connected bipolar transistor. The core also includes a first resistive network coupled between a base of the first diode-connected bipolar transistor and the reference terminal. An equalizer is configured to equalize potentials of the first terminal and of the second terminal and a voltage generator is coupled to the first and second terminals of the core and configured to generate the bandgap voltage.

公开(公告)号：US09892877B2

公开(公告)日：2018-02-13

申请号：US14657991

申请日：2015-03-13

Applicant: STMicroelectronics (Alps) SAS

Inventor： Vratislav Michal ,  Denis Cottin

IPC: H01H47/00 ,  H03K17/16 ,  H03K17/30

CPC classification number: H01H47/00 ,  H03K17/167 ,  H03K17/30 ,  H03K2017/307 ,  Y10T307/76

Abstract: A circuit including: a plurality of first switches connected in parallel between a first terminal and a second terminal; and a control circuit capable of implementing the following steps at each period of a clock signal: comparing the voltage between the first and second terminals with a reference voltage; if the voltage between the first and second terminals is greater than the reference voltage, turning on one of the first switches without modifying the state of the other switches; and if the voltage between the first and second terminals is smaller than the reference voltage, turning off one of the first switches without modifying the state of the other switches.

公开(公告)号：US20180004270A1

公开(公告)日：2018-01-04

申请号：US15253012

申请日：2016-08-31

Applicant: STMicroelectronics (Alps) SAS

Inventor： Fabien Journet

IPC: G06F1/32 ,  H04B5/00 ,  G06F1/10

CPC classification number: G06F1/324 ,  G06F1/06 ,  G06F9/3869 ,  H04B5/0037

Abstract: Dynamic power control embodiments concern a data processing pipeline. First and second pipeline stages respectively receive first and second clock signals. The first and second pipeline stages are configured to perform first and second operations respectively triggered by first timing edges of the first clock signal and second timing edges of the second clock signal. A clock controller is configured to generate the first and second clock signals. The clock controller is capable of operating in a first mode in which, during a first data processing cycle of the data processing pipeline, a first of the first timing edges is in-phase with a first of the second timing edges. The clock controller is also capable of operating in a second mode in which, during a second data processing cycle of the data processing pipeline, a second of the first timing edges is out of phase with a second of the second timing edges.

公开(公告)号：US09847798B2

公开(公告)日：2017-12-19

申请号：US14961996

申请日：2015-12-08

Applicant: STMicroelectronics (Alps) SAS ,  STMICROELECTRONICS (GRENOBLE 2) SAS

Inventor： Julien Saade ,  Abdelaziz Goulahsen

IPC: H04L27/00 ,  H04B1/04 ,  G06F13/42 ,  H04L25/49

CPC classification number: H04B1/04 ,  G06F13/4282 ,  H04L25/4908

Abstract: The invention relates to a method for serial data transmission, comprising the steps consisting in computing the running disparity (RD) of a bit stream that is being transmitted; when the running disparity reaches a threshold (T), computing a point disparity on a subsequent frame (S) of the stream; if the point disparity has the same sign as the threshold, inverting the states of the bits of the frame in the transmitted bit stream; and inserting into the transmitted bit stream a polarity bit having a state signalling the inversion.

公开(公告)号：US20170336819A1

公开(公告)日：2017-11-23

申请号：US15364392

申请日：2016-11-30

Applicant: STMicroelectronics (Alps) SAS

Inventor： Alexandre Pons

IPC: G05F1/59 ,  H02J7/02 ,  H01R24/60 ,  H03F3/45 ,  H02J7/06 ,  H02J7/10 ,  H01R107/00

CPC classification number: G05F1/59 ,  G05F1/56 ,  G05F1/569 ,  H01R24/60 ,  H01R2107/00 ,  H02J7/022 ,  H02J7/06 ,  H02J2007/10 ,  H03F3/45071 ,  H03F2203/45521 ,  H03F2203/45641

Abstract: A low dropout voltage regulator unit includes an error amplifier and a power stage having an output terminal that is looped back onto the error amplifier and is capable of delivering an output current to a load. The unit includes multiple main supply inputs that are intended to potentially receive, respectively, multiple different supply voltages. The power stage includes multiple power paths that are connected, respectively, between the main supply inputs and the output terminal, are individually selectable and each comprise an output transistor. The unit also includes a selector circuit connected to the main supply inputs and configured to select one of the power paths according to a selection criterion. The error amplifier includes an output stage configured to selectively control the output transistor of the selected power path.

公开(公告)号：US09813655B2

公开(公告)日：2017-11-07

申请号：US15237103

申请日：2016-08-15

Applicant: STMicroelectronics (Alps) SAS

Inventor： Serge Hembert

IPC: H03M1/12 ,  H04N5/44

CPC classification number: H04N5/44 ,  G09G5/006 ,  G09G2340/02 ,  G09G2370/20 ,  G09G2370/22 ,  H04R2420/05

Abstract: A video and/or audio decoder provided with a first terminal for supplying an analog audio and/or video signal, including: a first circuit capable of supplying a digital signal which is an image of said analog signal; a digital-to-analog converter capable of receiving as an input said digital signal; an amplifier coupling a second output terminal of the digital-to-analog converter to the first terminal; and a second circuit capable of comparing a signal representative of the voltage or current level on the first terminal with a reference signal, and of deducing therefrom whether the first terminal is connected or not to an analog input terminal of a video signal display and/or audio signal playing device.

公开(公告)号：US20170220443A1

公开(公告)日：2017-08-03

申请号：US15253002

申请日：2016-08-31

Applicant: STMicroelectronics (Alps) SAS

Inventor： Mickael Broutin ,  Benoit Lelievre ,  Nicolas Anquet

IPC: G06F11/27 ,  G06F11/07

CPC classification number: G06F11/27 ,  G06F11/0778 ,  G11C7/24 ,  G11C29/12 ,  G11C2029/3602

Abstract: Embodiments of the circuits described include a method wherein at least one command signal is activated. The activation of the at least one command signal causes a request to a testing circuit of a memory array to enter a memory test mode. The requested memory test mode permits at least part of the memory array to be read. In response to activation of the at least one command signal, a test control circuit initiates an overwrite sequence to overwrite the data stored in the memory array. The test control circuit enables the memory test mode once the overwrite sequence has been completed.

公开(公告)号：US09698183B2

公开(公告)日：2017-07-04

申请号：US14744482

申请日：2015-06-19

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Alps) SAS

Inventor： Nicolas Moeneclaey ,  Julien-Marc Roux ,  Jerome Bourgoin

IPC: H04N5/374 ,  H01L27/146 ,  H04N5/378 ,  H04N5/367 ,  H04N17/00 ,  H04N5/3745

CPC classification number: H01L27/14612 ,  H01L27/14643 ,  H04N5/367 ,  H04N5/374 ,  H04N5/3742 ,  H04N5/3745 ,  H04N5/378 ,  H04N17/002

Abstract: A CMOS image sensor including: an array of M×N pixels, the pixels of a same column being connected to a same output track, each pixel including a photodiode, a sense node, a transfer transistor, a reset transistor, and a read circuit; and a test circuit including an assembly of N elementary reference cells respectively connected to the N output tracks of the sensor, each cell including a resistor, a sense node, a transfer transistor, a reset transistor, and a read circuit, the N resistors being series-connected between first and second nodes of application of a reference voltage.

公开(公告)号：US20170179816A1

公开(公告)日：2017-06-22

申请号：US14975138

申请日：2015-12-18

Applicant: STMicroelectronics (Alps) SAS

Inventor： Vratislav MICHAL

IPC: H02M3/04

CPC classification number: H02M3/04 ,  H02M3/156 ,  H02M3/1588 ,  H02M2001/0054 ,  Y02B70/1466 ,  Y02B70/1491

Abstract: A method and apparatus for detecting a critical duty cycle that maximizes an output power of a boost converter is provided. In the method and apparatus, boost converter is operated may be operated at or below the critical duty cycle. In the method and apparatus, a first voltage that is a function of an output voltage of a boost converter and voltage drops across a first set of parasitic resistances of the boost converter is detected. A second voltage that is a function voltage drops across a second set of parasitic resistances of the boost converter is also detected. The voltages are compared to determine the critical duty cycle and the boost converter is operated in accordance with a duty cycle that does not exceed the critical duty cycle.