Abstract:
A new and advanced PWM current control is provided by a new method and control system architecture that achieve the very high performances of an advanced current control for full-bridge stages, in terms of accuracy, error, speed and frequency response, but with an outstandingly reduced complexity in terms of analog circuits required, comparable with that of an elementary peak current control. The only analog blocks required are one current sense transducer (i.e. a series resistor or a sense-FET) and one comparator for the current sensing while the rest of the control circuitry is digital.
Abstract:
In one embodiment, a light sensor includes four cell arrays, one for each color of the Bayer pattern, and four lenses each focusing the light coming from the scene to be captured on a respective cell array. The lenses are oriented such that at least a second green image, commonly provided by the fourth cell array, is both horizontally and vertically shifted (spaced) apart by half a pixel pitch from a first (reference) green image. In a second embodiment, the four lenses are oriented such that the red and blue images are respectively shifted (spaced) apart by half a pixel pitch from the first or reference green image, one horizontally and the other vertically, and the second green image is shifted (spaced) apart by half a pixel pitch from the reference green image both horizontally and vertically.
Abstract:
A device for stabilizing images acquired by a digital-image sensor includes a motion-sensing device, for detecting quantities correlated to pitch and yaw movements of the digital-image sensor, and a processing unit, connectable to the digital-image sensor for receiving a first image signal and configured for extracting a second image signal from the first image signal on the basis of the quantities detected by the motion-sensing device. The motion-sensing device includes a first accelerometer and a second accelerometer.
Abstract:
An insulated-gate transistor, includes a semiconductor material layer having a front surface, a body region, an insulated gate disposed over the body region with interposition of a gate dielectric, and a source and drain region, the source region formed in the body region and the drain region formed in the semiconductor material layer. The source and drain regions are spaced apart from each other by a channel zone in a portion of the body region underlying the insulated gate, and a charge carriers drift portion of the semiconductor material layer between the channel zone and the drain region, the insulated gate extending over the charge carriers drift portion. The drain region is located at a depth compared to the front surface for causing charge carriers to move in the charge carriers drift portion away from an interface between the semiconductor material layer and the gate dielectric.