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    DATA PROCESSOR
    131.
    发明专利
    DATA PROCESSOR 失效

    公开(公告)号：JPH04123230A

    公开(公告)日：1992-04-23

    申请号：JP24417990

    申请日：1990-09-14

    Applicant: HITACHI LTD

    Inventor： SUZUKI SHOJI ,  YAMAGUCHI SHINICHIRO ,  KUROSAWA KENICHI ,  KOBAYASHI YOSHIKI

    IPC: G06F9/38 ,  G06F15/16

    Abstract: PURPOSE:To efficiently execute plural programs in a high speed by fetching instructions to be simultaneously processed from the plural programs and simultaneously executing the fetched instructions. CONSTITUTION:Plural variable program counters 1021 to 1024 send instruction string fetching signals to a multiport instruction cache memory 101 through respective signal lines 1031 to 1034 and four instruction strings consisting of plural program instructions to be simultaneously executed and a system control instruction are fetched by four programs from the memory 101. The four fetched instruction strings are inputted to a plural-program instruction string fetching controller 15 through respective signal lines 11 to 14. The controller 15 sends the program execution instructions to respective decoders 601 to 608 through respective signal lines 21 to 28 and respective decoded instructions are connected to respective instruction execution units necessary for executing the instructions by an instruction execution unit connecting device 69. Thus, plural programs is efficiently executed in the high speed.

    COMPILE TYPE INFERENCE METHOD
    132.
    发明专利
    COMPILE TYPE INFERENCE METHOD 失效

    公开(公告)号：JPH0440527A

    公开(公告)日：1992-02-10

    申请号：JP14738490

    申请日：1990-06-07

    Applicant: HITACHI LTD ,  HITACHI INF SYST LTD

    Inventor： HIRAYAMA YOICHI ,  SHIMADA MASARU ,  KUROSAWA KENICHI ,  MORI SEIZO ,  ITO IKURO

    IPC: G06F9/44

    Abstract: PURPOSE:To eliminate the need of defining all of an enormous knowledge base of an inference object before the inference, and to execute the inference at a high speed with a compiled code by providing a means for generating and eliminating a frame on the way of the inference. CONSTITUTION:This method is constituted of a frame generating and eliminating means 1100 for generating or eliminating a dynamic frame, a dynamic frame data table 500 for storing the generated dynamic frame, and a dynamic frame part 400 having a machine language instruction train for referring to the dynamic frame and a control table 300 for managing its instruction train. Also, when both of a condition part of a rule and a static frame are not collated, the collation of the dynamic frame and the condition part is executed by the instruction train of the dynamic frame part 400. That is, when the frame is generated or eliminated by the frame generating and eliminating means 1100 in accordance with the variation of a state in the course of inference, it is eliminated to define in advance the frame to all enormous states. In such a manner, the compile type inference of a high speed can be attained.

    PARALLEL PROCESSING METHOD FOR PLURAL PATHS
    133.
    发明专利
    PARALLEL PROCESSING METHOD FOR PLURAL PATHS 失效

    公开(公告)号：JPH03214235A

    公开(公告)日：1991-09-19

    申请号：JP838490

    申请日：1990-01-19

    Applicant: HITACHI LTD

    Inventor： NAKATSUKA YASUHIRO ,  KUROSAWA KENICHI

    IPC: G06F9/38

    Abstract: PURPOSE:To extract the 100% parallelism out of a relevant program by preparing plural instruction taking-out parts. CONSTITUTION:When a breakup instruction is executed by a processing system, the instruction take-out means of other processing systems have accesses to an instruction cache memory 101 based on an instruction address set by a breakup instruction or an instruction address that is already set. Thus, the parallel processing can be carried on in each processing system despite an internal branching occurred in an instruction train during processing at each side. Meanwhile it is required again to select one of those processing systems that start their actions independently of each other. In such conditions, a merging instruction is executed by a single instruction executing means 105 (107). Thus, the actions of the instruction taking-out means of other processing systems are stopped. Then the operation of the means 105 (107) is also stopped. Consequently, the branching instructions themselves can also be executed in parallel with each other.

    INFERENCE OBJECT WORLD SWITCHING SYSTEM
    134.
    发明专利
    INFERENCE OBJECT WORLD SWITCHING SYSTEM 失效

    公开(公告)号：JPH02236635A

    公开(公告)日：1990-09-19

    申请号：JP5649189

    申请日：1989-03-10

    Applicant: HITACHI LTD

    Inventor： HIRAYAMA YOICHI ,  SHIMADA MASARU ,  KUROSAWA KENICHI ,  MORI SEIZO

    IPC: G06F9/44

    Abstract: PURPOSE:To continue inference even when a frame base(inference object world) is dynamically changed under the execution of the inference by providing ID information at every inference object world, and also switching the ID information when the inference object world is switched. CONSTITUTION:Three inference object worlds exist in a collation phase, and it is composed of the ID information which can decide a rule and a frame, the rule to perform collation and the frame being referred from the rule uniquely corresponding to an internal number in its word, respectively. Also, one ID information common area exists in a knowledge base, and an ID1 is stored in the common area since the inference is performed in the inference object world 1 at present. When the inference object world is switched from 1 to 2 in an execution phase, an ID2 is set in the common area. Thereby, it is possible to uniquely refer to the rule or the frame.

    PROLOG LANGUAGE COMPILER
    137.
    发明专利
    PROLOG LANGUAGE COMPILER 失效

    公开(公告)号：JPS62206638A

    公开(公告)日：1987-09-11

    申请号：JP4835786

    申请日：1986-03-07

    Applicant: HITACHI LTD

    Inventor： KUROSAWA KENICHI ,  ABE SHIGEO ,  KIRIYAMA KAORU ,  BANDO TADAAKI ,  NAKANISHI HIROAKI

    IPC: G06F9/45 ,  G06F9/44

    Abstract: PURPOSE:To attain a fast execution of a prolog processing system of an instruction system which operates exclusively a variable by using a sorting means that decides whether the variable should be allocated to a register or a memory. CONSTITUTION:For a prolog program A10, a sentence structure is analyzed through the sentence structure analysis A20 of a prolog compiler A and an intermediate word IA30 is outputted. The word IA30 is supplied to a logic variable sorting means A40. This means A40 contains a detecting means A410 for continuous execution part of clause and an identifying means A420 which identifies the variable emerging at the continuous execution part only in order to sort and set the register variables based on the gathering of incorporated predicates having a high emerging frequency and small processing load. The means A40 outputs an intermediate word IIA50 in response to the sorted variables. For such a word IIA50, an object program A70 containing a train of instruction codes is produced and outputted through the code production A60.

    PROLOGUE MACHINE
    138.
    发明专利
    PROLOGUE MACHINE 失效

    公开(公告)号：JPS6263341A

    公开(公告)日：1987-03-20

    申请号：JP20156285

    申请日：1985-09-13

    Applicant: HITACHI LTD

    Inventor： ABE SHIGEO ,  KUROSAWA KENICHI ,  KIRIYAMA KAORU ,  BANDO TADAAKI ,  NAKANISHI HIROAKI

    IPC: G06F9/44 ,  G06F9/22

    Abstract: PURPOSE:To prevent the increase of the capacity of firmware, by including the part of frequency used integral operation only in firmware by providing an instruction for numerical operation and discriminating tags and, at the time of loading point arithmetic, carrying out the operation by jumping to a software routine and returning the results to the firmware. CONSTITUTION:An instruction is read and decoded by means of an instruction decoding and operand fetching unit 10 and when, an operand is in a memory, the instruction is delivered to an executing unit 40 through a read out interface register 20. Regarding the content of a WCS 140, data of the address designated by the address of an MAR 110 are read out to an MIR 150 and the executing unit 40 is controlled in accordance with the content of the MIR 150. The content of the MAR 110 is increased by '1' by an adder 120 and, upon request, stored in a stack 130. The next address of the MAR 110 is selected by SEL 100. A selection controlling circuit 90 produces a control signal in accordance with the discriminated results of tag discriminating circuit 80 and 85 or other information.

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