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    Apparatus and method for managing data bias in a graphics processing architecture
    137.
    发明授权
    Apparatus and method for managing data bias in a graphics processing architecture 有权

    公开(公告)号：US10282811B2

    公开(公告)日：2019-05-07

    申请号：US15482685

    申请日：2017-04-07

    Applicant: Intel Corporation

    Inventor： Joydeep Ray ,  Abhishek R. Appu ,  Altug Koker ,  Balaji Vembu

    IPC: G09G5/36 ,  G06T1/20 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/0888 ,  G06F12/0875 ,  G06T1/60

    Abstract: An apparatus and method are described for managing data which is biased towards a processor or a GPU. For example, one embodiment of an apparatus comprises: a processor comprising one or more cores to execute instructions and process data, one or more cache levels, and cache coherence controllers to maintain coherent data in the one or more cache levels; a graphics processing unit (GPU) to execute graphics instructions and process graphics data, wherein the GPU and processor cores are to share a virtual address space for accessing a system memory; a GPU memory coupled to the GPU, the GPU memory addressable through the virtual address space shared by the processor cores and GPU; and bias management circuitry to store an indication, for each of a plurality of blocks of data, whether the data has a processor bias or a GPU bias, wherein if the data has a GPU bias, then the data is to be accessed by the GPU from the GPU memory without necessarily accessing the processor's cache coherence controllers and wherein requests for the data from the processor cores are processed as uncached requests, preventing the data from being cached in the one or more cache levels of the processor.

    AREA-EFFICIENT IMPLEMENTATIONS OF GRAPHICS INSTRUCTIONS
    139.
    发明申请
    AREA-EFFICIENT IMPLEMENTATIONS OF GRAPHICS INSTRUCTIONS 审中-公开

    公开(公告)号：US20190096024A1

    公开(公告)日：2019-03-28

    申请号：US15716280

    申请日：2017-09-26

    Applicant: Intel Corporation

    Inventor： Joydeep Ray ,  Prasoonkumar Surti ,  Abhishek R. Appu ,  Altug Koker ,  Vasanth Ranganathan

    IPC: G06T1/20 ,  G06F12/0875 ,  G06F12/1045 ,  G06F9/30 ,  G06T1/60 ,  G06T15/00

    Abstract: Embodiments are generally directed to area-efficient implementations of graphics instructions. An embodiment of an apparatus includes a graphics subsystem, the graphics subsystem including one or more of a first logic for processing of memory read-return data for single-instruction-multiple-data instructions, the first logic to store data for a message in raw data format and delay conversion into shader format until all cache line requests for the message have been received; a second logic for assembly of memory read-return data for media block instructions into shader register format, the logic to provide for storage of valid bytes from a cache fragment in a register; or a third logic to remap scatter or gather instructions to untyped surface instruction types. An embodiment of an apparatus includes a graphics subsystem, the graphics subsystem including a translation lookaside buffer (TLB) and a data port controller to control the TLB, the data port controller including an incoming request pipeline to receive an incoming request with virtual address and generate a response, an incoming response pipeline to receive the response and generate a cache request, and an invalidation flow pipeline.

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