公开(公告)号：WO2007091280A1

公开(公告)日：2007-08-16

申请号：PCT/IT2006/000061

申请日：2006-02-06

Applicant: STMICROELECTRONICS S.R.L. ,  FERRARA, Francesco ,  POMPA, Pier, Paolo ,  RINALDI, Ross

Inventor： FERRARA, Francesco ,  POMPA, Pier, Paolo ,  RINALDI, Ross

IPC: G01N21/64 ,  C12Q1/68

CPC classification number: G01N21/645 ,  C12Q1/6825 ,  G01N21/6445 ,  C12Q2561/119 ,  C12Q2523/313

Abstract: An optical apparatus for the inspection of nucleic acid probes includes: a holder (22) for housing a chip (1) for analysis of nucleic acids, containing nucleic acid probes (12, 12' ); a light (24), for supplying an excitation radiation (WE) to the holder (22); and an optical sensor (25) for detecting images (IMG) of the nucleic acid probes (12, 12'), when a chip (1) is housed in the holder (22). The light source (24) is configured for polarizing the excitation radiation (WE) according to a excitation polarization direction (DE). Furthermore, the apparatus is provided with a sensing polarizing filter (27), which is arranged so as to intercept a reflected portion (WR) of the excitation radiation (WE), directed towards the optical sensor (25). The sensing polarizing filter (27) has a direction of the sensing polarization (D3) transverse to the excitation polarization direction (DE).

Abstract translation: 用于检查核酸探针的光学装置包括：用于容纳用于核酸分析的芯片（1）的保持器（22），其包含核酸探针（12,12'）; 用于向所述保持器（22）提供激发辐射（WE）的光（24）; 以及当芯片（1）容纳在保持器（22）中时用于检测核酸探针（12,12'）的图像（IMG）的光学传感器（25）。 光源（24）被配置为根据激发偏振方向（DE）使激发辐射（WE）偏振。 此外，该装置设置有感测偏振滤光器（27），该感测偏振滤光器被布置成拦截朝向光学传感器（25）的激发辐射（WE）的反射部分（WR）。 感测偏振滤光器（27）具有横向于激发偏振方向（DE）的感测偏振方向（D3）。

公开(公告)号：WO2007006507A1

公开(公告)日：2007-01-18

申请号：PCT/EP2006/006675

申请日：2006-07-07

Applicant: STMICROELECTRONICS S.R.L. ,  FRISINA, Ferruccio ,  SAGGIO, Mario, Giuseppe

Inventor： FRISINA, Ferruccio ,  SAGGIO, Mario, Giuseppe

IPC: H01L21/04 ,  H01L29/78 ,  H01L29/24 ,  H01L29/423

CPC classification number: H01L29/7802 ,  H01L29/0634 ,  H01L29/1608 ,  H01L29/42368 ,  H01L29/66068

Abstract: Method for manufacturing a vertical power MOS transistor on a semiconductor substrate (10) with wide band gap comprising a first superficial semiconductor layer (11) with wide band gap of a first type of conductivity, comprising the steps of: forming trench regions (13) in the first superficial semiconductor layer (H), filling in said trench regions (13) by means of a second semiconductor layer (14) with wide band gap of a second type of conductivity, so as to form semiconductor portions (15) of the second type of conductivity contained in the first superficial semiconductor layer (11), carrying out at least one ion implantation of a first type of dopant in the semiconductor portions (15) for forming respective implanted body regions (19) of said second type of conductivity, carrying out at least one ion implantation of a second type of dopant in each of the implanted body regions (19) for forming at least one implanted source region (23) of the first type of conductivity inside the implanted body regions (19), carrying out an activation thermal process of the first and second type of dopant with low thermal budget suitable to complete said formation of the implanted body and source regions (19, 23).

Abstract translation: 一种用于制造具有宽带隙的半导体衬底（10）上的垂直功率MOS晶体管的方法，包括具有第一类型导电性的宽带隙的第一表面半导体层（11），包括以下步骤：形成沟槽区域（13） 在第一表面半导体层（H）中，通过具有第二导电类型的宽带隙的第二半导体层（14）填充所述沟槽区域（13），以形成第二半导体层 在第一表面半导体层（11）中包含的第二类导电体，在半导体部分（15）中进行至少一种第一类型掺杂剂的离子注入，用于形成所述第二导电类型的各个植入体区域（19） 在每个植入体区域（19）中进行至少一个第二类型掺杂剂的离子注入，用于在im内形成至少一个第一类型的电导率的注入源区（23） 植入体区域（19），以适合于完成植入体和源区（19,23）的所述形成的低热预算进行第一和第二类型掺杂剂的活化热处理。

公开(公告)号：WO2007006503A1

公开(公告)日：2007-01-18

申请号：PCT/EP2006/006671

申请日：2006-07-07

Applicant: STMICROELECTRONICS S.R.L. ,  SAGGIO, Mario, Giuseppe ,  FRISINA, Ferruccio ,  RASCUNA, Simone

Inventor： SAGGIO, Mario, Giuseppe ,  FRISINA, Ferruccio ,  RASCUNA, Simone

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/7802 ,  H01L29/0634 ,  H01L29/0886 ,  H01L29/1095 ,  H01L29/66712

Abstract: Process for manufacturing a power electronic device (30) comprising the following steps: forming a first semiconductor layer (21) of the first type of conductivity forming at least a second semiconductor layer (22) of a second type of conductivity value on the first semiconductor layer (21), forming, in this at least a second semiconductor layer (22), a first plurality of implanted regions (D1) of the first type of conductivity forming, above said at least a second semiconductor layer (22), a superficial semiconductor layer (26) of the first type of conductivity, forming in the surface semiconductor layer (26) body regions (40) of the second type of conductivity, the body regions (40) being aligned with portions of semiconductor layer (22) free from the plurality of said at least second implanted regions (D1), carrying out a thermal diffusion step so that the plurality of implanted regions (D1) form a plurality of electrically continuous implanted column regions (D).

Abstract translation: 一种用于制造功率电子器件（30）的方法，包括以下步骤：形成第一类型的导电性的第一半导体层（21），其形成至少第二类型的电导率值的第二半导体层（22），其在第一半导体 在所述至少第二半导体层（22）中形成所述第一类型的导电形成的第一多个注入区域（D1），在所述至少第二半导体层（22）之上，表面（21），表面 在所述表面半导体层（26）中形成所述第一导电类型的半导体层（26），所述半导体层（26）在所述第二导电类型的主体区域（40）中形成，所述主体区域（40）与半导体层 从所述多个所述至少第二注入区域（D1）中，进行热扩散步骤，使得所述多个注入区域（D1）形成多个电连续的注入区域（D）。

公开(公告)号：WO2006120221A1

公开(公告)日：2006-11-16

申请号：PCT/EP2006/062224

申请日：2006-05-10

Applicant: STMicroelectronics S.r.l. ,  SCURATI, Mario Giovanni

Inventor： SCURATI, Mario Giovanni

IPC: B81C1/00 ,  B01L3/00 ,  F04B19/00

CPC classification number: B01L3/50273 ,  B01L3/502707 ,  B01L3/502738 ,  B01L2200/10 ,  B01L2200/12 ,  B01L2300/0825 ,  B01L2300/087 ,  B01L2300/1827 ,  B01L2400/049 ,  B01L2400/0677 ,  Y10T29/49826 ,  Y10T137/0396 ,  Y10T137/2224

Abstract: A microfluidic device for nucleic acid analysis includes a monolithic semiconductor body (13), a microfluidic circuit (10), at least partially accommodated in the monolithic semiconductor body (13), and a micropump (11). The microfluidic circuit (10) includes a sample preparation channel (18) formed on the monolithic semiconductor body (13) and at least one microfluidic channel (20, 22) buried in the monolithic semiconductor body (13). The micropump (11), includes a plurality of sealed chambers (40) provided with respective openable sealing elements (41) and having a first pressure therein that is different from a second pressure in the microfluidic circuit (10). In addition, the micropump (11) and the microfluidic circuit (10) are configured so that opening the openable sealing elements (41) provides fluidic coupling between the respective chambers (40) and the microfluidic circuit (10). The openable sealing elements (41) are integrated in the monolithic semiconductor body (13).

Abstract translation: 用于核酸分析的微流体装置包括至少部分地容纳在单片半导体本体（13）中的单片半导体本体（13），微流体电路（10）和微型泵（11）。 微流体回路（10）包括形成在单片半导体本体（13）上的样品制备通道（18）和埋在单片半导体本体（13）中的至少一个微流体通道（20,22）。 微型泵（11）包括多个密封室（40），其设置有相应的可开启的密封元件（41），并且其中具有与微流体回路（10）中的第二压力不同的第一压力。 此外，微型泵（11）和微流体回路（10）构造成使得可打开的密封元件（41）的打开在各个腔室（40）和微流体回路（10）之间提供流体耦合。 可打开的密封元件（41）集成在单片半导体本体（13）中。

公开(公告)号：WO2006106556A1

公开(公告)日：2006-10-12

申请号：PCT/IT2006/000223

申请日：2006-04-04

Applicant: STMICROELECTRONICS S.R.L. ,  ZAPPA, Diego ,  FAZIO, Giuseppe ,  COLOMBO, Roberto

Inventor： ZAPPA, Diego ,  FAZIO, Giuseppe ,  COLOMBO, Roberto

IPC: G01N21/73 ,  H01J37/32

CPC classification number: H01J37/32972 ,  G01N21/73 ,  H01J37/32935

Abstract: A method for facilitating the determination of the end point of a dry plasma etching process of a material, is proposed. The method includes performing an analysis of the whole spectrum of a radiation generated during the plasma etching process of the material, the analysis comprising evaluating the time trend of a plurality of spectral components of the radiation, each spectral component indicating the time trend of the radiation intensity of a corresponding wavelengths interval of the radiation. The method further includes, on the basis of such analysis, selecting at least one of the spectral components, wherein the at least one spectral component has a time trend indicative of the evolution of the etching process of the material. The performing of the spectral analysis comprises performing a statistical analysis of the time trend of the whole spectrum of the radiation and, on the basis of the results of the statistical analysis, selecting the at least one spectral component.

Abstract translation: 提出了一种便于确定材料的干等离子体蚀刻工艺的终点的方法。 该方法包括对材料的等离子体蚀刻过程中产生的辐射的整个光谱进行分析，该分析包括评估辐射的多个光谱分量的时间趋势，每个光谱分量指示辐射的时间趋势 辐射的相应波长间隔的强度。 该方法还包括在这种分析的基础上，选择光谱分量中的至少一个，其中至少一个光谱分量具有指示材料的蚀刻过程演变的时间趋势。 光谱分析的执行包括对整个辐射光谱的时间趋势进行统计分析，并且基于统计分析的结果，选择至少一个光谱分量。

公开(公告)号：WO2006090417A1

公开(公告)日：2006-08-31

申请号：PCT/IT2005/000110

申请日：2005-02-28

Applicant: STMICROELECTRONICS S.R.L. ,  MASCOLO, Danilo ,  CEROFOLINI, Gianfranco

Inventor： MASCOLO, Danilo ,  CEROFOLINI, Gianfranco

IPC: H01L21/768 ,  B82B1/00

CPC classification number: B82Y10/00 ,  H01L21/76838 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention relates to a method for realising a nanometric circuit architecture (2) in a semiconductor device comprising the steps of: a) realising a plurality of active areas (1) on a substrate (A) of the semiconductor device; b) realising on the substrate (A) a seed layer (4) of a first material; c) realising a mask-spacer (5) of a second material on the seed layer (4) in a region (A’) of the substrate (A) comprised between said active areas (1), said mask-spacer (5) being realised by MSPT and having at least one end portion (5) extending over the region (A’); d) realising at least one mask (6) overlapping the mask-spacer (5) and extending in a substantially perpendicular direction thereto (5); e) selectively removing the seed layer (4) being exposed on the substrate (A); f) selectively removing the mask (6) and the mask-spacer (5) obtaining a seed-spacer (7; 70) comprising a linear portion (7a) extending in that region (A’) and connected to at least one portion (7b) being substantially orthogonal thereto; g) eventually realising at least one insulating spacer (8) from said seed-spacer (7; 70) through the MSPT, that at least one insulating spacer (8) reproducing at least part of the profile of said seed-spacer (7; 70); h) realising at least one nano-wire (3; 13; 23) of conductive material from the seed-spacer (7, 70) or from the at least one insulating spacer (8) through the MSPT, the at least one nano-wire (3; 13; 23; 33) comprising a first portion (3a; 13a) at least partially extending in said region (A’) and at least one second portion (3b; 13b) in contact with a respective active area (1), the second portion (3b; 13b) being substantially orthogonal to the first portion (3a; 13a).

Abstract translation: 本发明涉及一种在半导体器件中实现纳米电路结构（2）的方法，包括以下步骤：a）在半导体器件的衬底（A）上实现多个有源区（1）; b）在基板（A）上实现第一材料的种子层（4）; c）在所述有源区（1），所述掩模间隔物（5）之间的衬底（A）的区域（A'）中实现种子层（4）上的第二材料的掩模间隔物（5） 通过MSPT实现并且具有在区域（A'）上延伸的至少一个端部（5）; d）实现与所述掩模间隔件（5）重叠并沿基本垂直的方向（5）延伸的至少一个掩模（6）; e）选择性地去除暴露在基底（A）上的种子层（4）; f）选择性地去除掩模（6）和掩模间隔物（5），获得包括在该区域（A'）中延伸并连接到至少一个部分（A'）的直线部分（7a）的种子间隔物（7; 70） 7b）基本上与其正交; g）最终通过MSPT从所述种子间隔物（7; 70）中实现至少一个绝缘间隔物（8），至少一个绝缘间隔物（8）再现至少部分所述种子间隔物（7; 70）; h）从所述种子间隔物（7,70）或通过所述MSPT从所述至少一个绝缘间隔物（8）实现至少一个导电材料的纳米线（3; 13; 23），所述至少一个纳米线 包括在所述区域（A'）中至少部分地延伸的第一部分（3a; 13a）和与相应的有效区域（1）接触的至少一个第二部分（3b; 13b）的导线（3; 13; 23; 33） ），所述第二部分（3b; 13b）基本上与所述第一部分（3a; 13a）正交。

公开(公告)号：WO2006032622A1

公开(公告)日：2006-03-30

申请号：PCT/EP2005/054568

申请日：2005-09-14

Applicant: STMICROELECTRONICS S.R.L. ,  POZZI, Massimiliano ,  D'ANGELO, Gianfranco

Inventor： POZZI, Massimiliano ,  D'ANGELO, Gianfranco

IPC: B24B53/007 ,  B24B37/04

CPC classification number: B24B53/017

Abstract: The present invention refers to a multi-station rotary machine for polishing wafers, comprising a machine body (1) and a rotating tower (2) consisting of a plurality of heads (3) each of which supports a wafer (4). Said tower (2) made to rotate with predefined pitch between a first station (25) for loading/unloading the wafers (4) and subsequent work stations all the same in which said heads (3) position themselves on rotatable polishing plates (5) on which rotating cleaning arms (6) act in the work phase with rotation pin and rotating end (7) in contact with the above mentioned plates (5). Between said work stations intermediate washing zones of the heads (3) and the wafers (4) are provided for by means of cleaning means (8, 17) that comprise delivery blocks (8) of washing liquid positioned between said plates (5) and each one having an upper hole (9) for the delivery of a nozzle (11) spraying liquid under pressure for cleaning one of said heads (3) and the lower part of the tower (2), and a supplementary hole connected to a further nozzle (13) for cleaning the machine body (1) and the rotation pin of one of said cleaning arms (6). Said cleaning means also comprise arms (17) for delivering the washing liquid positioned above said plates (5) with external support and each one having a supplementary lower hole (20) connected to a tube (21) that carries the liquid towards a further nozzle (22) for cleaning the lower part of said rotating arms (6) when they are in the rest position.

Abstract translation: 本发明涉及一种用于抛光晶片的多工位旋转机，包括机体（1）和由多个头（3）组成的旋转塔（2），每个头（3）支撑晶片（4）。 所述塔架（2）在用于装载/卸载晶片（4）的第一工位（25）和所有头部（3）自身位于可旋转的抛光板（5）上的所有相同的工作站之间以预定的间距旋转， 在旋转销和与上述板（5）接触的旋转端（7）上，旋转清洁臂（6）在工作相中作用。 在所述工作站之间，通过清洁装置（8,17）提供头部（3）和晶片（4）的中间洗涤区域，所述清洁装置包括位于所述板（5）和 每个具有用于输送喷嘴（11）的喷嘴（11）的上孔（9），用于在压力下喷射液体以清洁所述头部（3）和塔架（2）的下部之一;以及辅助孔，其连接到另一个 用于清洁机体（1）的喷嘴（13）和所述清洁臂（6）之一的旋转销。 所述清洁装置还包括用于通过外部支撑件输送位于所述板（5）上方的洗涤液的臂（17），并且每个具有连接到管（21）的辅助下孔（20），所述管（21）将液体朝向另一个喷嘴 （22），用于当它们处于静止位置时清洁所述旋转臂（6）的下部。

公开(公告)号：WO2005093664A1

公开(公告)日：2005-10-06

申请号：PCT/IB2005/000117

申请日：2005-01-14

Applicant: STMICROELECTRONICS S.R.L. ,  GARDELLA, Pierluigi ,  BARONE, Massimiliano ,  GALLIZIO, Edoardo ,  PAU, Danilo

Inventor： GARDELLA, Pierluigi ,  BARONE, Massimiliano ,  GALLIZIO, Edoardo ,  PAU, Danilo

IPC: G06T11/40

CPC classification number: G06T11/40

Abstract: A system for rendering a primitive of an image to be displayed, for instance in a mobile 3D graphic pipeline, the primitive including a set of pixels. The system is configured for: - locating the pixels that fall within the area of the primitive, - generating, for each pixel located in the area, a set of associated sub-pixels, - borrowing a borrowed set of sub-pixels from neighboring pixels, - subjecting the set of associated sub-pixels and the borrowed set of pixels (A, B, C, D) to adaptive filtering to create an' adaptively filtered set of sub­pixels (AA, BB, CC, DD), and - subjecting at least the adaptively filtered set of sub-pixels (AA, BB, CC, DD) to further filtering to compute a final pixel adapted for display. Preferably, the set of associated sub-pixels fulfils at least one of the following requirements: the set includes two associated sub-pixels and - the set includes associated sub-pixels placed on triangle edges.

Abstract translation: 用于渲染要显示的图像的原语的系统，例如在移动3D图形流水线中，所述图元包括一组像素。 该系统被配置为： - 定位落在基元区域内的像素， - 为位于该区域中的每个像素产生一组相关联的子像素， - 从相邻像素借用借用的子像素组 - 对所述一组相关联的子像素和所借用的像素组（A，B，C，D）进行自适应滤波以创建“自适应滤波的子像素组（AA，BB，CC，DD）”，以及 - 至少自适应滤波的子像素组（AA，BB，CC，DD）进一步滤波以计算适于显示的最终像素。 优选地，该组相关联的子像素满足以下要求中的至少一个：该集合包括两个相关联的子像素，并且 - 该集合包括放置在三角形边缘上的相关联的子像素。

公开(公告)号：WO2005091481A1

公开(公告)日：2005-09-29

申请号：PCT/EP2005/050880

申请日：2005-03-01

Applicant: STMICROELECTRONICS S.R.L. ,  ADRAGNA, Claudio

Inventor： ADRAGNA, Claudio

IPC: H02M1/00

CPC classification number: H02M1/32

Abstract: The present invention relates to switching. power supplies, and especially to a method and the related circuit for protection against malfunctioning of the feedback loop in switching power supplies. More particularly it relates to a circuit for the identification of a condition of excessively high voltage at the output. In one embodiment the circuit for the protection against malfunctioning of the feedback loop of a switching power supply comprises: means for generating (vaux R1, R2) a voltage proportional to the output voltage of said switching power supply; a comparator (15) for comparing said voltage proportional to the output voltage with a reference voltage (vth); a counter (17) coupled to said comparator capable of supplying an output signal when said voltage proportional to the output voltage exceeds said reference voltage a preset number of times; said output signal is indicative of a malfunctioning of the feedback loop.

Abstract translation: 本发明涉及切换。 电源，特别是用于防止开关电源中的反馈回路故障的方法和相关电路。 更具体地说，涉及用于识别输出端的过高电压条件的电路。 在一个实施例中，用于防止开关电源的反馈回路故障保护的电路包括：用于产生与所述开关电源的输出电压成比例的电压的装置（vaux R1，R2） 比较器（15），用于将与输出电压成比例的所述电压与参考电压（vth）进行比较; 当与所述输出电压成比例的所述电压超过所述参考电压预定次数时，耦合到所述比较器的计数器（17）能够提供输出信号; 所述输出信号表示反馈回路的故障。

公开(公告)号：WO2005079053A1

公开(公告)日：2005-08-25

申请号：PCT/IT2005/000080

申请日：2005-02-16

Applicant: STMICROELECTRONICS S.R.L. ,  STMICROELECTRONICS LTD. ,  GARDELLA, Pier Luigi ,  BARONE, Massimiliano ,  SWEET, Gary ,  PAU, Danilo ,  HILL, Stephen? ,  GODA, Simon

Inventor： GARDELLA, Pier Luigi ,  BARONE, Massimiliano ,  SWEET, Gary ,  PAU, Danilo ,  HILL, Stephen? ,  GODA, Simon

IPC: H04N1/41

CPC classification number: H04N19/00 ,  G09G3/2051 ,  G09G5/02 ,  H04N1/40087 ,  H04N19/42 ,  H04N19/90

Abstract: An ordered dither method is applied to reduce the chromatic resolution of an image represented by channels R (red), G (green), B (blue) and A (brightness), whereby a first and a second dither matrix is provided, both comprising the same threshold values but arranged in a different spatial distribution. The first dither matrix is applied to the R, B, and A channels, and the second dither matrix is applied to the G channel.

Abstract translation: 应用有序抖动方法来降低由通道R（红色），G（绿色），B（蓝色）和A（亮度）表示的图像的色度分辨率，由此提供第一和第二抖动矩阵， 相同的阈值但排列在不同的空间分布。 第一个抖动矩阵被施加到R，B和A信道，第二个抖动矩阵被施加到G信道。