-
公开(公告)号：US11487314B2
公开(公告)日：2022-11-01
申请号：US17412816
申请日：2021-08-26
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor： Michael Giovannini
Abstract: An embodiment method for modifying the frequency of a clock signal clocking an integrated circuit supplied by a voltage controller comprises, in response to a command for the modification, varying the frequency of the clock signal at a rate allowing a supply voltage to be controlled by the controller. The variation comprises at least one series of successive divisions of the frequency of the clock signal into successive intermediate signals of respective intermediate frequencies.
-
公开(公告)号：US11469677B2
公开(公告)日：2022-10-11
申请号：US16906489
申请日：2020-06-19
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor： Jean Camiolo , Alexandre Pons
Abstract: The present disclosure relates to a voltage source device comprising: a voltage converter for generating a supply voltage at an output node of the voltage converter based on a feedback signal provided on a feedback line; at least one switch coupled between the output node of the voltage converter and an output terminal of the voltage source device; and at least one further switch configured to selectively couple the feedback line to: the output node of the voltage converter during a first regulation mode; and to the output terminal of the voltage source device during a second regulation mode.
-
公开(公告)号：US11460515B2
公开(公告)日：2022-10-04
申请号：US17123210
申请日：2020-12-16
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor： Vincent Pinon
Abstract: A circuit includes a voltage comparator with an output, a first input and a second input, the first input being coupled to a first reference voltage terminal. An operational transconductance amplifier has an output coupled to the second input of the voltage comparator, an inverting input coupled to the output of the operational transconductance amplifier, and a non-inverting input coupled to a second reference voltage terminal. A filter capacitor is coupled in series between a power supply terminal and the second input of the voltage comparator.
-
公开(公告)号：US20220312566A1
公开(公告)日：2022-09-29
申请号：US17654532
申请日：2022-03-11
Applicant: STMicroelectronics (Grenoble 2) SAS , STMicroelectronics S. r. l. , STMicroelectronics Application GMBH
Inventor： Manuel Gaertner , Philippe Sirito-Olivier , Giovanni Luca Torrisi , Thomas Urbitsch , Christophe Roussel , Fritz Burkhardt
IPC: H05B45/46 , H05B45/325 , H05B45/50 , H05B45/14
Abstract: A system includes lighting devices coupled to output supply pins, a microcontroller circuit, and a driver circuit, which receives data therefrom, and switches coupled in series to the lighting devices. The driver circuit includes output supply pins and selectively propagates a supply voltage to the output supply pins to provide respective pulse-width modulated supply signals at the output supply pins. The driver circuit computes duty-cycle values of the pulse-width modulated supply signals as a function of the data received from the microcontroller circuit. The lighting devices include at least one subset coupled to the same output supply pin. The microcontroller individually controls the switches via respective control signals to individually adjust a brightness of the lighting devices in the at least one subset of lighting devices.
-
公开(公告)号：US20220301649A1
公开(公告)日：2022-09-22
申请号：US17654918
申请日：2022-03-15
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor： Mark Trimmer
IPC: G11C29/10
Abstract: The present disclosure relates to a method wherein a state of an integrated circuit between a first state (e.g., CLOSED), allowing a reading access to the first area of fuse-type non-volatile memory by a processor, and a second state (e.g., OPEN), forbidding the reading access to the memory to the processor, is conditioned to a verification, by a finite state machine, of values of a first fuse word of the memory, representative of a number of transitions to the first state and of a second fuse word of the memory, representative of a number of transitions to the second state.
-
Patent Agency Ranking
公开(公告)号：US11451730B2
公开(公告)日：2022-09-20
申请号：US16890877
申请日：2020-06-02
Inventor： Pierre Malinge , Frederic Lalanne , Laurent Simony
IPC: H04N5/3745 , H04N5/355
Abstract: An image sensor includes pixels each including: a first transistor and a first switch that are connected in series between a first node configured to receive a first potential and an internal node of the pixel, a gate of the first transistor being coupled with a floating diffusion node of the pixel; a capacitive element, a first terminal of which is connected to the floating diffusion node of the pixel; and several assemblies each including a capacitance connected in series with a second switch coupling the capacitance to the internal node. The sensor also includes a control circuit configured to control, each time a voltage is stored in one of the assemblies of a pixel, an increase of a determined value of a difference in potential between the floating diffusion node and the internal node of the pixel.
-
147.发明申请公开(公告)号：US20220295007A1
公开(公告)日：2022-09-15
申请号：US17649858
申请日：2022-02-03
Inventor： Nicolas Moeneclaey , Samuel Foulon
IPC: H04N5/3745 , G01J1/42 , G01J1/44
Abstract: A photosensitive device includes a peripheral circuit semiconductor region, a photosensitive circuit semiconductor region including at least one group of at least two photosensitive elements configured to generate a photoelectric signal on a node called critical node. The device further includes an integrator circuit per group of photosensitive elements, each including: a differential circuit for each photosensitive element of the group, in the photosensitive circuit semiconductor region, an amplification circuit, in the peripheral circuit semiconductor region, and a feedback circuit for each photosensitive element of the group, comprising a capacitive element located in the photosensitive circuit semiconductor region coupled between the output node of the amplification circuit and the respective critical node.
-
公开(公告)号：US20220284954A1
公开(公告)日：2022-09-08
申请号：US17667080
申请日：2022-02-08
Inventor： Antonino Conte , Alin Razafindraibe , Francesco Tomaiuolo , Thibault Mortier
IPC: G11C13/00
Abstract: In an embodiment, a non-volatile memory device includes a memory array including a plurality of memory portions, each memory portion having a respective plurality of memory cells arranged in rows and columns, wherein the memory portions are arranged in groups, each group of memory portions having a plurality of respective memory portions arranged in a row and a plurality of respective wordlines that extend through the respective memory portions, and wherein the memory cells of the memory portions of the group are coupled to the respective wordlines and a row decoder including a pre-decoding stage configured to execute a selection, in which it selects a wordline that extends through a group of memory portions and deselects other wordlines that extend through the group of memory portions, and a subsequent deselection, in which it deselects all the wordlines that extend through the group of memory portions, wherein the row decoder further includes, for each group of memory portions, a shared pull-up stage configured to decouple from or couple to a node at a first reference potential each wordline that extends through the group of memory portions, when the wordline is respectively selected or deselected, so as to impose on each wordline, when deselected, a deselection voltage, a plurality of pull-down stages distributed along the group of memory portions, each pull-down stage being configured to locally couple each wordline that extends through the group of memory portions, when selected, to a node at a second reference potential, so as to impose locally a selection voltage on the wordline, wherein each pull-down stage is further configured to locally decouple from the node at the second reference potential each wordline that extends through the group of memory portions, when deselected; and a number of local pull-up stages distributed along the group of memory portions, each local pull-up stage having, for each wordline that extends through the group of memory portions, a corresponding local pull-up transistor of an NMOS type.
-
公开(公告)号：US20220239824A1
公开(公告)日：2022-07-28
申请号：US17571965
申请日：2022-01-10
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor： Giovanni Scozzola
Abstract: In an embodiment, a method for estimating a flicker frequency of a light source includes: obtaining, with a time-of-flight sensor, a profile of a light signal emitted by a light source; performing spectral analysis on the profile of the light signal emitted by the light source; and estimating a flicker frequency of the light source based on the spectral analysis of the profile of the light signal emitted by the light source.
-
公开(公告)号：US11387867B2
公开(公告)日：2022-07-12
申请号：US17322414
申请日：2021-05-17
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor： Giovanni Scozzola
Abstract: A microcontroller includes a plurality of electronic functional circuits comprising a read-only memory (ROM) and a central processing unit (CPU) and an interconnection circuit. The CPU and the interconnection circuit are disposed in a mobile electronic device and the ROM is disposed outside the mobile electronic device. The interconnection circuit is configured to communicate with the plurality of electronic functional circuits. The communication with the ROM is wireless communication.
-
-
-
-
-
-
-
-
-
Search Results
1362
records
(took 0.036 seconds)
