公开(公告)号：US20030223649A1

公开(公告)日：2003-12-04

申请号：US10360516

申请日：2003-02-07

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics Ltd.

Inventor： Keith Findlater ,  Robert Henderson ,  Stewart Smith ,  Jonathan Hurwitz ,  Mirko Guarnera

IPC: G06K009/32

CPC classification number: H04N5/374 ,  H04N5/3456 ,  H04N5/3458 ,  H04N9/045

Abstract: A digital camera for capturing and processing images of different resolutions and a corresponding method for down-scaling a digital image are provided. The method includes forming an image of a real scene on an image sensor that is made up of a plurality of pixels arranged in a matrix. The method further includes addressing and reading pixels in the matrix to obtain analog quantities related to the pixels luminance values, converting the analog quantities from the pixels matrix into digital values, and processing the digital values to obtain a data file representing the image of the real scene. To reduce computation time and power consumption, the addressing and reading of the pixels includes selecting a group of pixels from the matrix, and storing the analog quantities related to the pixels of the selected group of pixels into an analog storing circuit. The stored analog quantities are averaged to obtain an analog quantity corresponding to an average pixel luminance value.

Abstract translation: 提供了用于捕获和处理不同分辨率的图像的数字照相机和用于缩小数字图像的相应方法。 该方法包括在由矩阵排列的多个像素构成的图像传感器上形成真实场景的图像。 该方法还包括寻址和读取矩阵中的像素以获得与像素亮度值相关的模拟量，将来自像素矩阵的模拟量转换为数字值，并处理数字值以获得表示真实图像的数据文件 现场。 为了减少计算时间和功耗，像素的寻址和读取包括从矩阵中选择一组像素，并将与所选择的像素组的像素相关的模拟量存储到模拟存储电路中。 对存储的模拟量进行平均以获得对应于平均像素亮度值的模拟量。

公开(公告)号：US20030193595A1

公开(公告)日：2003-10-16

申请号：US10405904

申请日：2003-04-02

Applicant: STMicroelectronics Ltd

Inventor： Robert Henderson

IPC: H04N005/335

CPC classification number: H04N5/363 ,  H04N5/365 ,  H04N5/374 ,  H04N5/378

Abstract: An image sensor has an array of pixels. Each column has a first and a second column line connected to a read-reset amplifier/comparator which acts in a first mode as a unity gain buffer amplifier to reset the pixels via the first lines, and in a second mode acts as a comparator and AD converter to produce digitized reset and signal values. The reset and signal values are read out a line at a time in interleaved fashion. Reset values are stored in a memory and subsequently subtracted from the corresponding signal values. The arrangement reduces both fixed pattern and kT/C noise.

Abstract translation: 图像传感器具有像素阵列。 每列具有连接到以第一模式作为单位增益缓冲放大器的读 - 复位放大器/比较器的第一和第二列线，经由第一行复位像素，并且在第二模式中，作为比较器， AD转换器产生数字化复位和信号值。 复位和信号值以交错方式一次读出一行。 复位值存储在存储器中，并随后从相应的信号值中减去。 该装置减少固定模式和kT / C噪声。

公开(公告)号：US20020116426A1

公开(公告)日：2002-08-22

申请号：US10076116

申请日：2002-02-14

Applicant: STMicroelectronics Ltd.

Inventor： Parvesh Swami

IPC: G06F007/38

CPC classification number: G06F7/501 ,  G06F1/0356 ,  H03K19/17728

Abstract: A look-up table apparatus is provided for performing two-bit arithmetic operation including carry generation. The look-up table is modified to perform two concurrent combinatorial functions, or one function for an increased number of inputs. The look-up table of the present invention can implement two full adders or subtractors, or two-bit counters, for example. One portion of the modified look-up table provides two bits of a sum output, and another portion of the modified table provides a fast carry out signal for application to a next stage of an adder/subtractor/counter.

Abstract translation: 提供了一种用于执行包括进位产生的两比特算术运算的查找表装置。 查找表被修改为执行两个并发组合函数，或者一个增加数量的输入的函数。 本发明的查找表可以实现例如两个全加器或减法器或两位计数器。 经修改的查找表的一部分提供了和输出的两个比特，并且修改的表的另一部分提供了一个快速进位信号，用于应用于加法器/减法器/计数器的下一个级。

公开(公告)号：US20020097328A1

公开(公告)日：2002-07-25

申请号：US09939517

申请日：2001-08-24

Applicant: STMicroelectronics Ltd.

Inventor： Robert Henderson ,  Stewart Gresty Smith ,  Jonathan Ephriam David Hurwitz ,  Andrew Murray

IPC: H04N005/235

CPC classification number: H04N5/2357 ,  H04N5/235 ,  Y10S348/91

Abstract: Lighting flicker in the output of a video imaging device is detected. The video imaging device has a main picture area divided into pixels for producing successive images at a frame rate. A series of signals are produced from at least one additional picture area adjacent the main picture area, with the additional picture area having a size substantially larger than a pixel. Each of the signals is a function of light incident on the additional picture area in a time period substantially shorter than that of the frame rate. A predetermined number of the signals are accumulated to form a series of compound samples, and the compound samples are filtered to detect components indicating the lighting flicker. The filtering is performed using a bandpass filter tuned to the nominal flicker frequency. The compound samples are formed at a sample rate which is a multiple of the nominal flicker frequency, and the filtering is performed by taking the fundamental output component of a radix-N butterfly.

Abstract translation: 检测出影像成像装置的输出中的照明闪烁。 视频成像装置具有划分为像素的主图像区域，用于以帧速率产生连续的图像。 从与主图像区域相邻的至少一个附加图像区域产生一系列信号，其中附加图像区域的尺寸基本上大于像素。 每个信号是在比帧速率短的时间周期内入射到附加图像区域上的光的函数。 累积预定数量的信号以形成一系列化合物样品，并且过滤化合物样品以检测指示照明闪烁的组分。 使用调谐到标称闪烁频率的带通滤波器来执行滤波。 复合样本以标称闪烁频率的倍数的采样率形成，并且通过获取基数N蝶形的基本输出分量来执行滤波。

公开(公告)号：US20020048201A1

公开(公告)日：2002-04-25

申请号：US09948146

申请日：2001-09-06

Applicant: STMicroelectronics Ltd.

Inventor： Anurag Garg

IPC: G11C029/00

CPC classification number: G11C11/412 ,  G11C8/16

Abstract: A first-in, first-out (FIFO) memory cell architecture is provided in which one node of the latch in the FIFO memory cell is connected to the gate of the pass transistor. Further, the bit line is connected to the source of the pass transistor, and the word line is connected to the drain of the pass transistor to provide a stable memory cell requiring less area for implementation.

Abstract translation: 提供先入先出（FIFO）存储单元结构，其中FIFO存储单元中的锁存器的一个节点连接到传输晶体管的栅极。 此外，位线连接到传输晶体管的源极，并且字线连接到传输晶体管的漏极，以提供一个稳定的存储单元，其需要较少的实现面积。

公开(公告)号：US20010048341A1

公开(公告)日：2001-12-06

申请号：US09864946

申请日：2001-05-24

Applicant: STMicroelectronics Ltd.

Inventor： Kalyana Chakravarthy

IPC: H03B001/00

CPC classification number: H03K5/1252

Abstract: A glitch filter includes a storage element for storing a current state, which is the output of the filter. An output of the storage element is connected to one input of a state comparator. Another input of the state comparator is connected to an input signal. A programmable clock delay is connected between the state comparator and the storage element. The programmable clock delay may provide a programmed duration independent of the technology used for implementation. The glitch filter is arranged such that the input signal is stored as the new current state in the storage element only if the input signal changes and then remains unchanged for the programmed duration.

Abstract translation: 毛刺滤波器包括用于存储作为滤波器的输出的当前状态的存储元件。 存储元件的输出连接到状态比较器的一个输入。 状态比较器的另一输入端连接到输入信号。 在状态比较器和存储元件之间连接可编程时钟延迟。 可编程时钟延迟可以提供独立于用于实现的技术的编程时间。 毛刺滤波器被布置成使得仅当输入信号改变然后在编程的持续时间内保持不变时，才将输入信号作为新的当前状态存储在存储元件中。

公开(公告)号：US20250147626A1

公开(公告)日：2025-05-08

申请号：US19018944

申请日：2025-01-13

Applicant: STMICROELECTRONICS ( BEIJING) R&D CO. LTD ,  STMICROELECTRONICS LTD.

Inventor： Pengcheng Wen ,  Yuan Yun Wang

IPC: G06F3/041 ,  G06F3/044 ,  G09G3/3233

Abstract: A method of operating a display includes performing a non-synchronized touch scan pattern on a display with a controller coupled to the display. The non-synchronized touch scan pattern schedules touch scans independent of a refresh rate of the display. Upon the controller detecting a first synchronization pulse from a display controller coupled to the controller and the display, a first pulse-checking timer is started. Upon detecting a second synchronization pulse from the display controller and before the first pulse-checking timer expires, a first display refresh rate for the display is obtained from an interval between the first synchronization pulse and the second synchronization pulse. A synchronized touch scan pattern is performed with the controller, and is scheduled to avoid touch scans coinciding with refreshes of the display performed at the first display refresh rate.

公开(公告)号：US20250132690A1

公开(公告)日：2025-04-24

申请号：US18962653

申请日：2024-11-27

Applicant: STMICROELECTRONICS LTD

Inventor： Laurent GONTHIER

IPC: H02M7/155 ,  H02M1/42

Abstract: The present description concerns a converter comprising an AC-DC conversion stage comprising a first thyristor, a first power supply circuit delivering a first reference voltage between a first node and a second node, and a second power supply circuit delivering a second reference voltage between third and fourth nodes, the cathode of the first thyristor being coupled to the first node of the first power supply circuit by a first switch and being connected to the fourth node, the second power supply circuit comprising a first rectifying element coupled to the second node of the first power supply circuit and coupled to the third node.

公开(公告)号：US12184195B2

公开(公告)日：2024-12-31

申请号：US17736668

申请日：2022-05-04

Applicant: STMICROELECTRONICS LTD

Inventor： Laurent Gonthier

IPC: H02M7/155 ,  H02M1/42

Abstract: The present description concerns a converter comprising an AC-DC conversion stage comprising a first thyristor, a first power supply circuit delivering a first reference voltage between a first node and a second node, and a second power supply circuit delivering a second reference voltage between third and fourth nodes, the cathode of the first thyristor being coupled to the first node of the first power supply circuit by a first switch and being connected to the fourth node, the second power supply circuit comprising a first rectifying element coupled to the second node of the first power supply circuit and coupled to the third node.

公开(公告)号：US20230412084A1

公开(公告)日：2023-12-21

申请号：US18209744

申请日：2023-06-14

Applicant: STMicroelectronics LTD

Inventor： Laurent GONTHIER

IPC: H02M3/335 ,  H02M3/315

CPC classification number: H02M3/33571 ,  H02M3/315

Abstract: The present description concerns a circuit for converting from a first alternating voltage to a second voltage. The circuit includes: a first thyristor; a first control circuit of the first thyristor; a power factor correction circuit comprising a coil; and a first circuit configured to convert a third voltage into a fourth DC voltage. The third voltage corresponds to a difference between a potential at a first node connected to an output node of the coil and a reference potential. The fourth DC voltage is configured to supply the first control circuit of the first thyristor, and is referenced with respect to the same reference potential as the third voltage.