公开(公告)号：US20140183685A1

公开(公告)日：2014-07-03

申请号：US14144168

申请日：2013-12-30

Applicant: Commissariat à I'Énergie Atomique et aux Énergies Alternatives ,  STMicroelectronics S.A.

Inventor： François Roy ,  Yvon Cazaux

IPC: H01L27/146

CPC classification number: H01L27/14603 ,  H01L27/14614 ,  H01L27/1463 ,  H01L27/14656

Abstract: An image sensor arranged inside and on top of a semiconductor substrate, having a plurality of pixels, each including: a photosensitive area, a read area, and a storage area extending between the photosensitive area and the read area; at least one first insulated vertical electrode extending in the substrate between the photosensitive area and the storage area; and at least one second insulated vertical electrode extending in the substrate between the storage area and the read area.

Abstract translation: 布置在半导体衬底的内部和顶部的具有多个像素的图像传感器，每个像素包括：感光区域，读取区域和在感光区域和读取区域之间延伸的存储区域; 至少一个第一绝缘垂直电极，其在所述基板中在所述光敏区域和所述存储区域之间延伸; 以及在所述存储区域和所述读取区域之间的所述衬底中延伸的至少一个第二绝缘垂直电极。

公开(公告)号：US20140151768A1

公开(公告)日：2014-06-05

申请号：US13692716

申请日：2012-12-03

Applicant: STMICROELECTRONICS S.A.

Inventor： Ullrich Pfeiffer ,  Hani Sherry ,  Andreia Cathelin

IPC: H01L27/146

CPC classification number: H01L27/14612 ,  G01N21/3581 ,  G01S7/352 ,  G01S13/887 ,  G01V8/005

Abstract: A pixel circuit including: a differential detection circuit having first and second transistors coupled in series between differential output nodes of an antenna, the antenna being configured to be sensitive to terahertz radiation, and wherein: a first main conducting node of the first transistor is coupled to a first of the differential output nodes of the antenna; and a first main conducting node of the second transistor is coupled to a second of said differential output nodes of the antenna, wherein second main conducting nodes of the first and second transistors are formed by a common semiconductor region.

Abstract translation: 一种像素电路，包括：差分检测电路，其具有串联耦合在天线的差分输出节点之间的第一和第二晶体管，所述天线被配置为对太赫兹辐射敏感，并且其中：所述第一晶体管的第一主导电节点被耦合 到天线的差分输出节点中的第一个; 并且所述第二晶体管的第一主导电节点耦合到所述天线的所述差分输出节点中的第二个，其中所述第一和第二晶体管的第二主导体节点由公共半导体区域形成。

公开(公告)号：US20140103972A1

公开(公告)日：2014-04-17

申请号：US14050203

申请日：2013-10-09

Applicant: MentorGraphics Corporation ,  STMicroelectronics S.A.

Inventor： Anna Asquini ,  Vincent Vallet

IPC: H03K3/017

CPC classification number: H03K3/017 ,  G06F1/10 ,  G06F1/12 ,  H03K5/1252

Abstract: A duty cycle protection circuit including a first synchronous device adapted to receive a first clock signal on an input line and to generate a first clock transition of a second clock signal in response to a first clock transition of the first clock signal; and reset circuitry coupled to the input line and adapted to generate a second clock transition of the second clock signal by resetting the first synchronous device a time delay after the first clock transition of the first clock signal.

Abstract translation: 一种占空比保护电路，包括适于在输入线路上接收第一时钟信号的第一同步装置，并且响应于第一时钟信号的第一时钟转换而产生第二时钟信号的第一时钟转变; 以及复位电路，其耦合到所述输入线并且适于通过在所述第一时钟信号的所述第一时钟转换之后复位所述第一同步器件时间延迟来产生所述第二时钟信号的第二时钟转变。

公开(公告)号：US20130335666A1

公开(公告)日：2013-12-19

申请号：US13920206

申请日：2013-06-18

Applicant: Commissariat a I'Energie Atomique et aux Energies Alternatives ,  STMicroelectronics S.A.

Inventor： Michel Marty ,  Flavien Hirigoyen ,  Josep Segura Puchades ,  Hélène Wehbe-Alause ,  Umberto Rossini

IPC: G02F1/1368 ,  H01L33/36

CPC classification number: G02F1/1368 ,  G02F1/136209 ,  G02F1/136213 ,  G02F1/136277 ,  G02F2001/136281 ,  H01L33/36

Abstract: A nanoprojector panel formed of an array of cells, each cell including a liquid crystal layer between upper and lower transparent electrodes, a MOS control transistor being arranged above the upper electrode, each transistor being covered with at least three metallization levels. The transistor of each cell extends in a corner of the cell so that the transistors of an assembly of four adjacent cells are arranged in a central region of the assembly. The upper metallization level extends above the transistors of each the assembly of four adjacent cells. The panel includes, for each assembly of four adjacent cells, a first conductive ring surrounding the transistors, the first ring extending from the lower metallization level to the upper electrode of each cell, with an interposed insulating material.

Abstract translation: 一种由单元阵列形成的纳米光电板面板，每个单元包括上透明电极和下透明电极之间的液晶层，MOS控制晶体管布置在上电极上方，每个晶体管被覆盖有至少三个金属化水平。 每个单元的晶体管延伸在单元的角部，使得四个相邻单元的组件的晶体管被​​布置在组件的中心区域中。 上部金属化水平延伸到四个相邻单元的每个组件的晶体管之上。 对于四个相邻电池的每个组件，面板包括围绕晶体管的第一导电环，第一环从下部金属化层延伸到每个电池的上部电极，并具有插入的绝缘材料。

公开(公告)号：US20130181785A1

公开(公告)日：2013-07-18

申请号：US13745634

申请日：2013-01-18

Applicant: STMicroelectronics S.A. ,  International Business Machines Corporation

Inventor： Yvan Morandini ,  Romain Debrouke

IPC: H03B28/00 ,  H03H11/00

CPC classification number: H03B28/00 ,  H03B5/12 ,  H03B5/1212 ,  H03B5/1228 ,  H03B5/1253 ,  H03B5/1265 ,  H03H11/00 ,  H03J3/20

Abstract: A variable capacitance device including: first and second transistors coupled in series by their main current nodes between first and second nodes of the device, a control node of the first transistor being adapted to receive a first control signal, and a control node of the second transistor being adapted to receive a second control signal; and control circuitry adapted to generate the first and second control signals from a selection signal.

Abstract translation: 一种可变电容器件，包括：第一和第二晶体管，其由器件的第一和第二节点之间的主要电流节点串联连接，第一晶体管的控制节点适于接收第一控制信号，第二晶体管的控制节点 晶体管适于接收第二控制信号; 以及适于从选择信号产生第一和第二控制信号的控制电路。

公开(公告)号：US20040257008A1

公开(公告)日：2004-12-23

申请号：US10812843

申请日：2004-03-30

Applicant: STMicroelectronics S.A.

Inventor： Jean-Michel Moreau

IPC: G09G001/04

CPC classification number: H04N3/16

Abstract: The invention concerns a scanning circuit, comprising a power supply providing a negative voltage on a first terminal (Tdown), an intermediate voltage on a second terminal (Gnd) and a positive voltage on a terminal of a switch (S), the other terminal of the switch being connected to a third terminal (Tup), a control circuit (6) supplied by connections to the second and third terminals, a differential amplifier receiving a positive and a negative input signal provided by the control circuit, a power amplifier controlled by the differential amplifier, both amplifiers being supplied by connections to the first and third terminals, a deflection coil (Ly) connected between the output of the power amplifier and the second terminal, biasing means setting, when the switch is open, the output of the differential amplifier so that the possible current paths through the power amplifier between the deflection coil and the first terminal are cut.

Abstract translation: 本发明涉及一种扫描电路，包括在第一端子（Tdown）上提供负电压的电源，第二端子上的中间电压（Gnd）和开关（S）的端子上的正电压，另一个端子 所述开关连接到第三端子（Tup），通过连接到所述第二和第三端子提供的控制电路（6），接收由所述控制电路提供的正和负输入信号的差分放大器，控制的功率放大器 通过差分放大器，通过连接到第一和第三端子的两个放大器提供连接在功率放大器的输出端和第二端子之间的偏转线圈（Ly），当开关断开时，偏置装置设定输出 差分放大器，使得穿过偏转线圈和第一端子之间的功率放大器的可能电流路径被切断。

公开(公告)号：US20040252536A1

公开(公告)日：2004-12-16

申请号：US10862057

申请日：2004-06-04

Applicant: STMicroelectronics S.A.

Inventor： Richard Ferrant

IPC: G11C027/00

CPC classification number: G11C15/04

Abstract: A CAM cell with masking made in the form of an integrated circuit, including a first storage cell including a first transistor, first and second inverters in anti-parallel, and a second transistor; a comparison cell, including third and fourth transistors controlling a fifth transistor, connected in series with a sixth inhibiting transistor to a result line; and a second storage cell, including a seventh transistor in series with two inverters in anti-parallel and an eighth transistor, the second storage cell controlling the inhibiting transistor. The first, second, seventh, and eighth transistors may be N-channel transistors, and the third, fourth, fifth, and sixth transistors may be P-channel transistors.

Abstract translation: 具有以集成电路形式形成的掩蔽的CAM单元，包括：第一存储单元，包括第一晶体管，反并联的第一和第二反相器以及第二晶体管; 比较单元，包括控制第五晶体管的第三和第四晶体管，与第六抑制晶体管串联连接到结果行; 以及第二存储单元，其包括与反并联的两个反相器串联的第七晶体管和第八晶体管，所述第二存储单元控制所述抑制晶体管。 第一，第二，第七和第八晶体管可以是N沟道晶体管，并且第三，第四，第五和第六晶体管可以是P沟道晶体管。

公开(公告)号：US20040218439A1

公开(公告)日：2004-11-04

申请号：US10766291

申请日：2004-01-26

Applicant: STMicroelectronics S.A.

Inventor： Michel Harrand ,  Joseph Bulone

IPC: G11C007/00

CPC classification number: G11C11/40615 ,  G11C11/406 ,  G11C2211/4061

Abstract: The content of a few pages of the dynamic random access memory is backed up, then one tries to refresh them less quickly, for example two times less quickly, and one observes whether this does or does not cause errors. The operation is repeated on the entire memory. Depending on the number of errors that have appeared on the pages refreshed less often, the refresh period is decreased or increased. Thus, the memory self-adjusts its refresh period to what is necessary for it.

Abstract translation: 对动态随机存取存储器的几页内容进行备份，然后尝试快速刷新它们，例如快速刷新两次，一次观察是否会导致错误。 在整个存储器上重复操作。 根据刷新页面上出现的错误次数不同，刷新周期减少或增加。 因此，内存将自己的刷新周期自动调整到需要的时间。

公开(公告)号：US20040217305A1

公开(公告)日：2004-11-04

申请号：US10778323

申请日：2004-02-13

Applicant: STMicroelectronics S.A.

Inventor： Jean-Pierre Schoellkopf ,  Herve Jaouen

IPC: G21G005/00

CPC classification number: H01L21/76807 ,  H01L21/76801 ,  H01L23/522 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of repairing a defect in an integrated electronic circuit caused by an incorrect lithographic mask includes the formation of an electrical isolation between two conducting parts of the circuit. The electrical isolation is obtained by at least partly filling, with an electrically insulating material, a volume hollowed out beforehand which would otherwise, and incorrectly, form an electrical connection between the two conducting parts. To do this, a mask having an aperture revealing the hollowed out volume is formed on the circuit, and the mask used to direct the filling of the electrically insulating material and correction of the lithography defined defect.

Abstract translation: 修复由不正确的光刻掩模引起的集成电子电路中的缺陷的方法包括在电路的两个导电部分之间形成电隔离。 电隔离是通过用电绝缘材料至少部分地填充预先挖空的体积获得的，否则并且不正确地在两个导电部件之间形成电连接。 为此，在电路上形成具有露出掏空体积的孔径的掩模，以及用于引导电绝缘材料的填充的掩模和校正光刻限定的缺陷。

公开(公告)号：US20040213035A1

公开(公告)日：2004-10-28

申请号：US10775032

申请日：2004-02-09

Applicant: STMicroelectronics S.A.

Inventor： Paola Cavaleri ,  Bruno Leconte ,  Sebastien Zink

IPC: G11C011/00

CPC classification number: G11C16/3431 ,  G11C16/16 ,  G11C16/3418 ,  G11C16/349

Abstract: The present invention relates to a method for controlling and for refreshing memory cells in an electrically erasable and programmable memory comprising a memory array organized in sectors, each sector comprising memory cells linked to bit lines and to word lines. The method comprises controlling and refreshing memory cells of pages of the memory array the address of which is indicated by a control and refresh counter comprising data forming tokens usable once. According to the present invention, a control and refresh counter is integrated into each sector of the memory and comprises memory cells linked to the bit lines of the sector. A counter of a sector is erased after reaching a maximum counting value that is chosen so that, when this maximum counting value is reached, memory cells of the counter have undergone a number of electrical stress cycles that is at the most equal to a determined number. Application to Flash memories.

Abstract translation: 本发明涉及一种用于控制和刷新电可擦除可编程存储器中的存储器单元的方法，该存储器单元包括以扇区组织的存储器阵列，每个扇区包括链接到位线和字线的存储器单元。 该方法包括控制和刷新存储器阵列的存储单元，其存储单元的地址由包括可使用一次的令牌的数据形成的控制和刷新计数器指示。 根据本发明，控制和刷新计数器被集成到存储器的每个扇区中，并且包括链接到扇区的位线的存储器单元。 在达到选择的最大计数值之后擦除扇区的计数器，使得当达到该最大计数值时，计数器的存储单元已经经历了多个等于确定数量的电应力循环 。 应用于闪存。