公开(公告)号：KR1019940003845B1

公开(公告)日：1994-05-03

申请号：KR1019910007109

申请日：1991-05-02

Applicant: 한국전자통신연구원 ,  주식회사 케이티

Inventor： 한태만 ,  조주현 ,  김화성 ,  임동선

IPC: H04M3/00

Abstract: The processor employing the method improves the reliability of error process and speeds up the process. The method employs a low level main board (1), a low level interface boards (2,8) which comprises GPIP and DDR, a hardware units(12 or 15) which connect low level interface board to TD-bus(6). The method includes a lst step (102) which selects one of hardware units (15 or 17) via a parameter, a 2nd step (104) which reads or writes a registor of GPIR and assigns GPIR to hardware port address (103), a 3rd step which assigns DDR to hardware signal and data input-output direction, and a 4th step which selects a bus through bits 4,7.

Abstract translation: 采用该方法的处理器提高了错误处理的可靠性，并加快了处理速度。 该方法采用低级主板（1），包含GPIP和DDR的低级接口板（2,8），将低级接口板连接到TD总线（6）的硬件单元（12或15）。 该方法包括经由参数选择硬件单元（15或17）中的一个的第一步骤（102），读取或写入GPIR的转换器并将GPIR分配给硬件端口地址（103）的第二步骤（104） 将DDR分配给硬件信号和数据输入输出方向的第三步，以及通过位4,7选择总线的第四步。

公开(公告)号：KR1019920022751A

公开(公告)日：1992-12-19

申请号：KR1019910007109

申请日：1991-05-02

Applicant: 한국전자통신연구원 ,  주식회사 케이티

Inventor： 한태만 ,  조주현 ,  김화성 ,  임동선

IPC: H04M3/00

Abstract: 내용 없음.