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公开(公告)号：US10733693B2
公开(公告)日：2020-08-04
申请号：US16208715
申请日：2018-12-04
Applicant: Intel Corporation
Inventor： Travis Schluessler , Zack Waters , Michael Apodaca , Jason Surprise , Peter Doyle
Abstract: Embodiments described herein provide data processing device comprising a processor, a memory, and a large draw monitor comprising a processing unit to determine whether a vertex count for a graphics workload exceeds a threshold value, and in response to a determination that the vertex count for the graphics workload exceeds the threshold value, to divide the graphics workload over graphics processing units instantiated on multiple separate tiles. Other embodiments may be described and claimed.
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公开(公告)号：US10706591B2
公开(公告)日：2020-07-07
申请号：US16142866
申请日：2018-09-26
Applicant: Intel Corporation
Inventor： Karthik Vaidyanathan , Prasoonkumar Surti , Hugues Labbe , Atsuo Kuwahara , Sameer Kp , Jonathan Kennedy , Murali Ramadoss , Michael Apodaca , Abhishek Venkatesh
Abstract: Systems, apparatuses and methods may provide for technology that determines a stencil value and uses the stencil value to control, via a stencil buffer, a coarse pixel size of a graphics pipeline. Additionally, the stencil value may include a first range of bits defining a first dimension of the coarse pixel size and a second range of bits defining a second dimension of the coarse pixel size. In one example, the coarse pixel size is controlled for a plurality of pixels on a per pixel basis.
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公开(公告)号：US20200004329A1
公开(公告)日：2020-01-02
申请号：US16515315
申请日：2019-07-18
Applicant: Intel Corporation
Inventor： Altug Koker , Michael Apodaca , Kai Xiao , Chandrasekaran Sakthivel , Jeffery S. Boles , Adam T. Lake , James M. Holland , Pattabhiraman K , Sayan Lahiri , Radhakrishnan Venkataraman , Kamal Sinha , Ankur N. Shah , Deepak S. Vembar , Abhishek R. Appu , Joydeep Ray , Elmoustapha Ould-Ahmed-Vall
IPC: G06F3/01 , G06T15/00 , G06T3/40 , G06T1/60 , G06F3/16 , G06F3/147 , G06T19/00 , G06F3/0481 , G06T7/80
Abstract: Systems, apparatuses and methods may provide away to enhance an augmented reality (AR) and/or virtual reality (VR) user experience with environmental information captured from sensors located in one or more physical environments. More particularly, systems, apparatuses and methods may provide a way to track, by an eye tracker sensor, a gaze of a user, and capture, by the sensors, environmental information. The systems, apparatuses and methods may render feedback, by one or more feedback devices or display device, for a portion of the environment information based on the gaze of the user.
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公开(公告)号：US10430147B2
公开(公告)日：2019-10-01
申请号：US15489096
申请日：2017-04-17
Applicant: Intel Corporation
Inventor： Deepak S. Vembar , Atsuo Kuwahara , Chandrasekaran Sakthivel , Radhakrishnan Venkataraman , Brent E. Insko , Anupreet S. Kalra , Hugues Labbe , Altug Koker , Michael Apodaca , Kai Xiao , Jeffery S. Boles , Adam T. Lake , David M. Cimini , Balaji Vembu , Elmoustapha Ould-Ahmed-Vall , Jacek Kwiatkowski , Philip R. Laws , Ankur N. Shah , Abhishek R. Appu , Joydeep Ray , Wenyin Fu , Nikos Kaburlasos , Prasoonkumar Surti , Bhushan M. Borole
Abstract: An embodiment of a graphics apparatus may include a processor, memory communicatively coupled to the processor, and a collaboration engine communicatively coupled to the processor to identify a shared graphics component between two or more users in an environment, and share the shared graphics components with the two or more users in the environment. Embodiments of the collaboration engine may include one or more of a centralized sharer, a depth sharer, a shared preprocessor, a multi-port graphics subsystem, and a decode sharer. Other embodiments are disclosed and claimed.
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公开(公告)号：US10402345B2
公开(公告)日：2019-09-03
申请号：US15337128
申请日：2016-10-28
Applicant: Intel Corporation
Inventor： Michael Apodaca
IPC: G06F12/00 , G06F12/126 , G06F12/0891 , G06F12/0875 , G06F3/048 , G06F12/12
Abstract: An apparatus comprises a processor to perform tile-based rendering to build a command buffer without knowledge whether the contents of a cache will be discarded, and a memory to store the command buffer. The processor is to determine a discard state of the cache prior to executing the command buffer, execute the command buffer, and discard or keep the contents of the cache according to the discard state. The command buffer can sample discard control from memory immediately before the processor executes the command buffer. The discard control in memory can be updated after the command buffer is queued and before the processor executes the command buffer.
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Patent Agency Ranking
公开(公告)号：US10192281B2
公开(公告)日：2019-01-29
申请号：US15204402
申请日：2016-07-07
Applicant: Intel Corporation
Inventor： Jeffery S. Boles , Hema C. Nalluri , Balaji Vembu , Pritav H. Shah , Michael Apodaca , Murali Ramadoss , Lalit K. Saptarshi
Abstract: A mechanism for command stream processing is described. A method of embodiments, as described herein, includes fetching cache lines from a memory to fill command first in first out buffer (FIFO), wherein the fetched cachelines an overfetching of data necessary to process a command, a first parser to fetch and execute batch commands stored in the command FIFO and a second parser to fetch commands and execute the batch commands and non-batch commands stored in the command FIFO.
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147.发明申请公开(公告)号：US20180308277A1
公开(公告)日：2018-10-25
申请号：US15494778
申请日：2017-04-24
Applicant: Intel Corporation
Inventor： Prasoonkumar Surti , Karthik Vaidyanathan , Atsuo Kuwahara , Hugues Labbe , Sameer Kp , Jonathan Kennedy , Abhishek R. Appu , Jeffery S. Boles , Balaji Vembu , Michael Apodaca , Slawomir Grajewski , Gabor Liktor , David M. Cimini , Andrew T. Lauritzen , Travis T. Schluessler , Murali Ramadoss , Abhishek Venkatesh , Joydeep Ray , Kai Xiao , Ankur N. Shah , Altug Koker
CPC classification number: G06T15/405 , G06T1/20 , G06T11/40 , G06T15/005 , G06T15/30 , G06T15/40 , G06T17/20 , G06T2210/52
Abstract: The systems, apparatuses and methods may provide a way to adaptively process and aggressively cull geometry data. Systems, apparatuses and methods may provide for processing, by a positional only shading pipeline (POSH), geometry data including surface triangles for a digital representation of a scene. More particularly, systems, apparatuses and methods may provide a way to identify surface triangles in one or more exclusion zones and non-exclusion zones, and cull surface triangles surface triangles in one or more exclusion zones.
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公开(公告)号：US10109078B1
公开(公告)日：2018-10-23
申请号：US15483701
申请日：2017-04-10
Applicant: Intel Corporation
Inventor： Karthik Vaidyanathan , Prasoonkumar Surti , Hugues Labbe , Atsuo Kuwahara , Sameer Kp , Jonathan Kennedy , Murali Ramadoss , Michael Apodaca , Abhishek Venkatesh
Abstract: Systems, apparatuses and methods may provide for technology that determines a stencil value and uses the stencil value to control, via a stencil buffer, a coarse pixel size of a graphics pipeline. Additionally, the stencil value may include a first range of bits defining a first dimension of the coarse pixel size and a second range of bits defining a second dimension of the coarse pixel size. In one example, the coarse pixel size is controlled for a plurality of pixels on a per pixel basis.
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149.发明申请公开(公告)号：US20180300940A1
公开(公告)日：2018-10-18
申请号：US15488837
申请日：2017-04-17
Applicant: Intel Corporation
Inventor： Chandrasekaran Sakthivel , Michael Apodaca , Kai Xiao , Altug Koker , Jeffery S. Boles , Adam T. Lake , Nikos Kaburlasos , Joydeep Ray , John H. Feit , Travis T. Schluessler , Jacek Kwiatkowski , James M. Holland , Prasoonkumar Surti , Jonathan Kennedy , Louis Feng , Barnan Das , Narayan Biswal , Stanley J. Baran , Gokcen Cilingir , Nilesh V. Shah , Archie Sharma , Mayuresh M. Varerkar
CPC classification number: G06T15/06 , G06F3/011 , G06F3/012 , G06F3/013 , G06F3/017 , G06T15/005 , G06T15/04 , G06T15/80 , G06T17/10 , G06T19/006 , G06T2215/16 , H04S7/304 , H04S2400/01 , H04S2400/11 , H04S2400/15 , H04S2420/01 , H04S2420/11
Abstract: Systems, apparatuses and methods may provide away to render augmented reality and virtual reality (VR/AR) environment information. More particularly, systems, apparatuses and methods may provide a way to selectively suppress and enhance VR/AR renderings of n-dimensional environments. The systems, apparatuses and methods may deepen a user's VR/AR experience by focusing on particular feedback information, while suppressing other feedback information from the environment.
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公开(公告)号：US20180299952A1
公开(公告)日：2018-10-18
申请号：US15488666
申请日：2017-04-17
Applicant: Intel Corporation
Inventor： Altug Koker , Michael Apodaca , Kai Xiao , Chandrasekaran Sakthivel , Jeffery S. Boles , Adam T. Lake , James M. Holland , Pattabhiraman K , Sayan Lahiri , Radhakrishnan Venkataraman , Kamal Sinha , Ankur N. Shah , Deepak S. Vembar , Abhishek R. Appu , Joydeep Ray , Elmoustapha Ould-Ahmed-Vall
CPC classification number: G06F3/013 , G06F3/011 , G06F3/016 , G06F3/04815 , G06F3/147 , G06F3/167 , G06T1/60 , G06T3/40 , G06T7/80 , G06T15/005 , G06T19/006 , G06T2200/28
Abstract: Systems, apparatuses and methods may provide away to enhance an augmented reality (AR) and/or virtual reality (VR) user experience with environmental information captured from sensors located in one or more physical environments. More particularly, systems, apparatuses and methods may provide a way to track, by an eye tracker sensor, a gaze of a user, and capture, by the sensors, environmental information. The systems, apparatuses and methods may render feedback, by one or more feedback devices or display device, for a portion of the environment information based on the gaze of the user.
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