公开(公告)号：US11716826B2

公开(公告)日：2023-08-01

申请号：US16402055

申请日：2019-05-02

Applicant: Intel Corporation

Inventor： Telesphor Kamgaing ,  Johanna M. Swan ,  Georgios Dogiamis ,  Henning Braunisch ,  Adel A. Elsherbini ,  Aleksandar Aleksov ,  Richard Dischler

IPC: H05K7/14 ,  H05K1/02 ,  H01P5/12 ,  H01P3/16 ,  H01L23/00 ,  H01L25/18 ,  H01L23/66 ,  H01L23/538 ,  H05K1/18

CPC classification number: H05K7/1489 ,  H01P3/16 ,  H01P5/12 ,  H05K1/0243 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/66 ,  H01L24/16 ,  H01L25/18 ,  H01L2223/6616 ,  H01L2223/6627 ,  H01L2224/16225 ,  H05K1/181 ,  H05K2201/10356 ,  H05K2201/10378 ,  H05K2201/10734

Abstract: Embodiments may relate an electronic device that includes a first platform and a second platform coupled with a chassis. The platforms may include respective microelectronic packages. The electronic device may further include a waveguide coupled to the first platform and the second platform such that their respective microelectronic packages are communicatively coupled by the waveguide. Other embodiments may be described or claimed.

公开(公告)号：US11664303B2

公开(公告)日：2023-05-30

申请号：US17375360

申请日：2021-07-14

Applicant: Intel Corporation

Inventor： Johanna Swan ,  Henning Braunisch ,  Aleksandar Aleksov ,  Shawna Liff ,  Brandon Rawlings ,  Veronica Strong

IPC: H01L23/498 ,  G03F1/38 ,  G03F1/54 ,  G03F1/68

CPC classification number: H01L23/49838 ,  G03F1/38 ,  G03F1/54 ,  G03F1/68 ,  H01L23/49827 ,  H01L23/49866

Abstract: An lithographic reticle may be formed comprising a transparent substrate, a substantially opaque mask formed on the transparent substrate that defines at least one exposure window, wherein the at least one exposure window has a first end, a first filter formed on the transparent substrate within the at least one exposure window and abutting the first end thereof, and a second filter formed on the transparent substrate within the at least one exposure window and abutting the first filter, wherein an average transmissivity of the first filter is substantially one half of a transmissivity of the second filter. In another embodiment, the at least one exposure window includes a third filter abutting the second end and is adjacent the second filter. Further embodiments of the present description include interconnection structures and systems fabricated using the lithographic reticle.

公开(公告)号：US20230099827A1

公开(公告)日：2023-03-30

申请号：US17484281

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Aleksandar Aleksov ,  Feras Eid ,  Wenhao Li ,  Stephen Morein ,  Yoshihiro Tomita

IPC: H01L23/532 ,  H01L21/768

Abstract: Technologies for high throughput additive manufacturing (HTAM) structures are disclosed. In one embodiment, a sacrificial dielectric is formed to provide a negative mask on which to pattern a conductive trace using HTAM. In another embodiment, a permanent dielectric is patterned using a processing such as laser project patterning. A conductive trace can then be patterned using HTAM. In yet another embodiment, conductive traces with tapered sidewalls can be patterned, and then a buffer layer and HTAM layer can be deposited on top.

公开(公告)号：US20230098020A1

公开(公告)日：2023-03-30

申请号：US17484384

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Feras Eid ,  Aleksandar Aleksov ,  Henning Braunisch ,  Adel Elsherbini ,  Thomas L. Sounart ,  Johanna Swan

IPC: H01L23/473 ,  H01L23/50 ,  H05K7/20 ,  H01L23/31

Abstract: Technologies for cooling conformal power delivery structures are disclosed. In one embodiment, an integrated circuit component has a die with a backside power plane mated to it. A lid of the integrated circuit component is mated with the backside power plane, forming a sealed cavity. The lid has an inlet and an outlet, and a channel is defined in the lid for liquid coolant to flow from the inlet, across the backside power plane, and to the outlet. The liquid coolant directly contacts the backside power plane, efficiently removing heat from the backside power plane.

公开(公告)号：US20230095846A1

公开(公告)日：2023-03-30

申请号：US17485039

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Benjamin T. Duong ,  Srinivas V. Pietambaram ,  Aleksandar Aleksov ,  Helme Castro De La Torre ,  Kristof Darmawikarta ,  Darko Grujicic ,  Sashi S. Kandanur ,  Suddhasattwa Nad ,  Rengarajan Shanmugam ,  Thomas I. Sounart ,  Marcel A. Wall

IPC: H01L23/498 ,  H01G4/33 ,  H01L21/48

Abstract: Glass substrates having transverse capacitors for use with semiconductor packages and related methods are disclosed. An example semiconductor package includes a glass substrate having a through glass via between a first surface and a second surface opposite the first surface. A transverse capacitor is located in the through glass via. The transverse capacitor includes a dielectric material positioned in a first portion of the through glass via, a first barrier/seed layer positioned in a second portion of the through glass via, and a first conductive material positioned in a third portion of the through glass via.

公开(公告)号：US20230095654A1

公开(公告)日：2023-03-30

申请号：US17484213

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Feras Eid ,  Stephen Morein ,  Krishna Bharath ,  Henning Braunisch ,  Beomseok Choi ,  Brandon M. Rawlings ,  Thomas L. Sounart ,  Johanna Swan ,  Yoshihiro Tomita ,  Aleksandar Aleksov

IPC: H01L23/498 ,  H01L23/48 ,  H01L25/065 ,  H01L21/48

Abstract: In one embodiment, a conformal power delivery structure includes a first electrically conductive layer comprising metal. The first electrically conductive layer defines one or more recesses, and the conformal power delivery structure also includes a second electrically conductive layer comprising metal that is at least partially within the recesses of the first electrically conductive layer. The second electrically conductive layer has a lower surface that generally conforms with the upper surface of the first electrically conductive layer. The conformal power delivery structure further includes a dielectric material between the surfaces of the first electrically conductive layer and the second electrically conductive layer that conform with one another.

公开(公告)号：US20230094686A1

公开(公告)日：2023-03-30

申请号：US17485034

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Kristof Darmawikarta ,  Srinivas V. Pietambaram ,  Aleksandar Aleksov

IPC: H01L23/522 ,  H01L23/15 ,  H01L23/528 ,  H01L23/50 ,  H01L21/768

Abstract: Glass layers having partially embedded conductive layers for power delivery in semiconductor packages and related methods are disclosed. An example semiconductor package includes a core layer having a thickness between a first surface opposite a second surface. The core layer includes a trench provided in the first surface. The trench partially extending between the first surface and the second surface. An electrically conductive material is positioned in the trench. A trace is provided on the conductive material. The trace is offset in a direction away from the first surface and away from the second surface of the core layer.

公开(公告)号：US11605867B2

公开(公告)日：2023-03-14

申请号：US17344715

申请日：2021-06-10

Applicant: Intel Corporation

Inventor： Brandon C. Marin ,  Jeremy D. Ecton ,  Aleksandar Aleksov ,  Kristof Darmawikarta ,  Yonggang Li ,  Dilan Seneviratne

IPC: H01P1/208 ,  H01P1/20 ,  H01P7/10 ,  H01L23/66 ,  H01P3/16 ,  H01L21/768 ,  H01P11/00 ,  H01L21/288

Abstract: A method of fabricating an RF filter on a semiconductor package comprises forming a first dielectric buildup film. A second dielectric buildup film is formed over the first dielectric buildup film, the second dielectric buildup film comprising a dielectric material that contains a metallization catalyst, wherein the dielectric material comprises one of an epoxy-polymer blend dielectric material, silicon dioxide and silicon nitride, and a low-k dielectric. A trench is formed in the second dielectric buildup film with laser ablation, wherein the laser ablation selectively activates sidewalls of the trench for electroless metal deposition. A metal selectively is plated to sidewalls of the trench based at least in part on the metallization catalyst and immersion in an electroless solution. A low-loss buildup film is formed over the metal that substantially fills the trench.

公开(公告)号：US20220415837A1

公开(公告)日：2022-12-29

申请号：US17359380

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Kimin Jun ,  Feras Eid ,  Adel Elsherbini ,  Aleksandar Aleksov ,  Shawna Liff ,  Johanna Swan ,  Julien Sebot

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/31 ,  H01L21/56 ,  H01L25/00

Abstract: Techniques and mechanisms for mitigating stress on hybrid bonded interfaces in a multi-tier arrangement of integrated circuit (IC) dies. In an embodiment, first dies are bonded at a host die each via a respective one of first hybrid bond interfaces, wherein a second one or more dies are coupled to the host die each via a respective one of the first dies, and via a respective second hybrid bond interface. Stress at one of the hybrid bond interfaces is mitigated by properties of a first dielectric layer that extends to that hybrid bond interface. In another embodiment, stress at a given one of the hybrid bond interfaces is mitigated by properties of a dummy chip—or alternatively, properties of a patterned encapsulation structure—which is formed on the given hybrid bond interface.

公开(公告)号：US11460499B2

公开(公告)日：2022-10-04

申请号：US16573946

申请日：2019-09-17

Applicant: Intel Corporation

Inventor： Henning Braunisch ,  Aleksandar Aleksov ,  Veronica Strong ,  Brandon Rawlings ,  Johanna Swan ,  Shawna Liff

IPC: H01L23/498 ,  H01L23/538 ,  H01L23/31 ,  G01R31/28 ,  G01K7/42 ,  G01K7/02

Abstract: An integrated circuit package having an electronic interposer comprising an upper section, a lower section and a middle section, a die side integrated circuit device electrically attached to the upper section of the electronic interposer, a die side heat dissipation device thermally contacting the die side integrated circuit device, a land side integrated circuit device electrically attached to the lower section of the electronic interposer, and a land side heat dissipation device thermally contacting the at least one die side integrated circuit device. The upper section and the lower section may each have between two and four layers and the middle section may be formed between the upper section and the lower section, and comprises up to eight layers, wherein a thickness of each layer of the middle section is thinner than a thickness of any of the layers of the upper section and the lower section.