公开(公告)号：US20180308285A1

公开(公告)日：2018-10-25

申请号：US15494696

申请日：2017-04-24

Applicant: Intel Corporation

Inventor： Peter L. Doyle ,  Devan Burke ,  Subramaniam Maiyuran ,  Abhishek R. Appu ,  Joydeep Ray ,  Elmoustapha Ould-Ahmed-Vall ,  Philip R. Laws ,  Altug Koker

IPC: G06T17/20 ,  G06T15/80 ,  G06T15/00

CPC classification number: G06T17/20 ,  G06T15/005 ,  G06T15/04 ,  G06T15/80 ,  G06T17/10 ,  G06T17/205

Abstract: Systems, apparatuses and methods may provide a way to subdivide a patch generated in graphics processing pipeline into sub-patches, and generate sub-patch tessellations for the sub-patches. More particularly, systems, apparatuses and methods may provide a way to diverge tessellation sizes to a configurable size within an interior region of a patch or sub-patches based on a position of each of the tessellations. The systems, apparatuses and methods may determine a number of tessellation factors to use based on one or more of a level of granularity of one or more domains of a scene to be digitally rendered, available computing capacity, or power consumption to compute the number of tessellation factors.

公开(公告)号：US20180308267A1

公开(公告)日：2018-10-25

申请号：US15494594

申请日：2017-04-24

Applicant: Intel Corporation

Inventor： Joydeep Ray

IPC: G06T11/60 ,  G06T7/194 ,  G06T1/20

CPC classification number: G06T11/60 ,  G06T1/20 ,  G06T7/194 ,  G06T2200/28 ,  G06T2207/20008

Abstract: Video or graphics, received by a render engine within a graphics processing unit, may be segmented into a region of interest such as foreground and a region of less interest such as background. In other embodiments, an object of interest may be segmented from the rest of the depiction in a case of a video game or graphics processing workload. Each of the segmented portions of a frame may themselves make up a separate surface which is sent separately from the render engine to the display engine of a graphics processing unit. In one embodiment, the display engine combines the two surfaces and sends them over a display link to a display panel. The display controller in the display panel displays the combined frame. The combined frame is stored in a buffer and refreshed periodically. In accordance with another embodiment, video or graphics may be segmented by a render engine into regions of interest or objects of interest and objects not of interest and again each of the separate regions or objects may be transferred to the display engine as a separate surface. Then the display engine may transfer the separate surfaces to a display controller of a display panel over a display link. At the display panel, a separate frame buffer may be used for each of the separate surfaces.

公开(公告)号：US20180308212A1

公开(公告)日：2018-10-25

申请号：US15493324

申请日：2017-04-21

Applicant: Intel Corporation

Inventor： Kiran C. Veernapu ,  Abhishek R. Appu ,  Prasoonkumar Surti ,  Arijit Mukhopadhyay ,  Altug Koker ,  Joydeep Ray

IPC: G06T1/60 ,  G06T1/20

CPC classification number: G06T1/60 ,  G06T1/20 ,  G06T2210/08

Abstract: A mechanism is described for facilitating selective skipping of compression cycles in computing devices. A method of embodiments, as described herein, includes facilitating determining a first current output relating to compression of a current set of data to be same as a previous output from compression of a previous set of data, and turning off a compression engine to skip compression of the current set of data.

公开(公告)号：US20180308207A1

公开(公告)日：2018-10-25

申请号：US15798574

申请日：2017-10-31

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Altug Koker ,  Linda L. Hurd ,  Dukhwan Kim ,  Mike B. Macpherson ,  John C. Weast ,  Feng Chen ,  Farshad Akhbari ,  Narayan Srinivasa ,  Nadathur Rajagopalan Satish ,  Joydeep Ray ,  Ping T. Tang ,  Michael S. Strickland ,  Xiaoming Chen ,  Anbang Yao ,  Tatiana Shpeisman

IPC: G06T1/20

CPC classification number: G06T1/20 ,  G06F9/3001 ,  G06F9/3017 ,  G06F9/3851 ,  G06F9/3887 ,  G06F9/3895 ,  G06F9/46 ,  G06N3/063 ,  G06T15/005 ,  G06T15/04 ,  G09G5/363

Abstract: An apparatus to facilitate compute optimization is disclosed. The apparatus includes sorting logic to sort processing threads into thread groups based on bit depth of floating point thread operations.

公开(公告)号：US20180308202A1

公开(公告)日：2018-10-25

申请号：US15495054

申请日：2017-04-24

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Altug Koker ,  John C. Weast ,  Mike B. Macpherson ,  Linda L. Hurd ,  Sara S. Baghsorkhi ,  Justin E. Gottschlich ,  Prasoonkumar Surti ,  Chandrasekaran Sakthivel ,  Liwei Ma ,  Elmoustapha Ould-Ahmed-Vall ,  Kamal Sinha ,  Joydeep Ray ,  Balaji Vembu ,  Sanjeev Jahagirdar ,  Vasanth Ranganathan ,  DUKHWAN Kim

IPC: G06T1/20 ,  G06N3/08

CPC classification number: G06T1/20 ,  G06N3/08

Abstract: A mechanism is described for facilitating inference coordination and processing utilization for machine learning at autonomous machines. A method of embodiments, as described herein, includes detecting, at training time, information relating to one or more tasks to be performed according to a training dataset relating to a processor including a graphics processor. The method may further include analyzing the information to determine one or more portions of hardware relating to the processor capable of supporting the one or more tasks, and configuring the hardware to pre-select the one or more portions to perform the one or more tasks, while other portions of the hardware remain available for other tasks.

公开(公告)号：US20180308198A1

公开(公告)日：2018-10-25

申请号：US15493522

申请日：2017-04-21

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Balaji Vembu ,  Altug Koker ,  Bryan R. White ,  David J. Cowperthwaite ,  Joydeep Ray ,  Murali Ramadoss

IPC: G06T1/20 ,  G06F9/50 ,  G06F9/455

Abstract: An apparatus to facilitate partitioning of a graphics device is disclosed. The apparatus includes a plurality of engines and logic to partition the plurality of engines to facilitate independent access to each engine within the plurality of engines.

公开(公告)号：US20180308197A1

公开(公告)日：2018-10-25

申请号：US15493420

申请日：2017-04-21

Applicant: Intel Corporation

Inventor： Balaji Vembu ,  Murali Ramadoss ,  Guei-Yuan Lueh ,  Subramaniam M. Maiyuran ,  Abhishek R. Appu ,  Joydeep Ray ,  Altug Koker ,  James A. Valerio ,  Eric J. Hoekstra ,  Arthur D. Hunter, JR.

IPC: G06T1/20 ,  G06F9/22 ,  G06F9/44 ,  G06T15/04

CPC classification number: G06T1/20 ,  G06F9/223 ,  G06F9/4496 ,  G06T15/04

Abstract: An apparatus to facilitate data intelligent dispatching is disclosed. The apparatus includes one or more processing units including a plurality of execution units (EUs) to execute a plurality of processing threads and collection logic to collect statistics data for threads executed at the processing unit during execution of an application, and dispatch logic to dispatch the threads to be executed at a subset of the plurality of EUs during a subsequent execution of the application based on the statistics data.

公开(公告)号：US20180308196A1

公开(公告)日：2018-10-25

申请号：US15493352

申请日：2017-04-21

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Abhishek R. Appu ,  Subramaniam M. Maiyuran ,  Eric J. Hoekstra ,  Prasoonkumar Surti ,  Balaji Vembu ,  Altug Koker

IPC: G06T1/20 ,  G06F9/48 ,  G06F9/50

CPC classification number: G06T1/20 ,  G06F9/4831 ,  G06F9/4881 ,  G06F9/505 ,  G06T2210/52

Abstract: A mechanism is described for facilitating thread execution arbitration for thread scheduling relating to graphics processors at computing devices. A method of embodiments, as described herein, includes assigning priority levels to threads based on stall signals communicated from the one or more shared function units to one or more execution units of a processor including a graphics processor, and selecting a first thread to be scheduled and a second thread to be ignored based on the stall signals.

公开(公告)号：US20180307984A1

公开(公告)日：2018-10-25

申请号：US15494971

申请日：2017-04-24

Applicant: Intel Corporation

Inventor： Altug Koker ,  Abhishek R. Appu ,  Kamal Sinha ,  Joydeep Ray ,  Balaji Vembu ,  Elmoustapha Ould-Ahmed-Vall ,  Sara S. Baghsorkhi ,  Anbang Yao ,  Kevin Nealis ,  Xiaoming Chen ,  John C. Weast ,  Justin E. Gottschlich ,  Prasoonkumar Surti ,  Chandrasekaran Sakthivel ,  Farshad Akhbari ,  Nadathur Rajagopalan Satish ,  Liwei Ma ,  Jeremy Bottleson ,  Eriko Nurvitadhi ,  Travis T. Schluessler ,  Ankur N. Shah ,  Jonathan Kennedy ,  Vasanth Ranganathan ,  Sanjeev Jahagirdar

IPC: G06N3/08 ,  G06N99/00

CPC classification number: G06N3/08 ,  G06F9/28 ,  G06F9/505 ,  G06N3/0445 ,  G06N3/0454 ,  G06N3/0481 ,  G06N3/063 ,  G06N99/005

Abstract: In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to analyze a workload and assign the workload to one of the first type of execution unit or the second type of execution unit. Other embodiments are also disclosed and claimed.

公开(公告)号：US20180307295A1

公开(公告)日：2018-10-25

申请号：US15493243

申请日：2017-04-21

Applicant: Intel Corporation

Inventor： Mohammed Tameem ,  Altug Koker ,  Kiran C. Veernapu ,  Abhishek R. Appu ,  Ankur N. Shah ,  Joydeep Ray ,  Travis T. Schluessler ,  Jonathan Kennedy

IPC: G06F1/32 ,  G06F13/16 ,  G06F13/40

Abstract: Described herein are various embodiments of reducing dynamic power consumption within a processor device. One embodiment provides a technique for dynamic link width reduction based on the instantaneous throughput demand for client of an interconnect fabric. One embodiment provides for a parallel processor comprising an interconnect fabric including a dynamic bus module to configure a bus width for a client of the interconnect fabric based on throughput demand from the client.