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公开(公告)号：BR9105222A
公开(公告)日：1993-06-01
申请号：BR9105222
申请日：1991-12-02
Applicant: MOTOROLA INC
Inventor： FREEBURG THOMAS A , WARREN CHARLES L
IPC: H04B7/00
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公开(公告)号：MX165383B
公开(公告)日：1992-11-06
申请号：MX1678089
申请日：1989-07-12
Applicant: MOTOROLA INC
Inventor： FREEBURG THOMAS A
Abstract: A communication system for relatively high data bit rate RF communication overcomes multipath interference by employing relatively narrow beam antenna sectors and by selecting the best communication path established between two terminals (110, 120), at least one of which has narrow beam antenna sectors (1-6). The communication path selection process includes determining the signal integrity (380) of data communicated between the terminals. One implementation includes the narrow beam antenna sectors (16 & A-F) at each terminal.
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公开(公告)号：NZ236320A
公开(公告)日：1992-10-28
申请号：NZ23632090
申请日：1990-12-03
Applicant: MOTOROLA INC
Inventor： FREEBURG THOMAS A , KACZMARCZYK JOHN M , BUCHHOLZ DALE R , WHITE RICHARD E , CHANG HUNGKUN J , NOLAN MICHAEL P
Abstract: In this invention a hierarchical addressing technique is employed in a packet communications system to enhance flexibility in handling packet information. This method permits packet message data (Fig. 3) and certain packet control data (Fig. 3) to be stored in memory locations (32, 34) without having to be duplicated at a different memory location prior to transmission of the packet. This method is preferably employed in a ring configuration in which a series of packets have addressing mechanisms which points sequentially to each other to form a ring of packets.
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公开(公告)号：BR9200101A
公开(公告)日：1992-10-06
申请号：BR9200101
申请日：1992-01-15
Applicant: MOTOROLA INC
Inventor： CHANG HUNGKUN J , DOSS WILLIAM K , NOLAN MICHAEL P , BUCCHOLZ DALE R , FREEBURG THOMAS A , MCKOWN JOHN , WHITE RICHARD E
Abstract: An antenna selection technique is used in an RF communication system in which user modules (UM1-UM5) communicate with at least one node (N1-N2). The UM's (UM1-UM5) and nodes (N1, N2) each have multiple antennae. The combination of each UM and node antenna is evaluated at the UM. Based on at least signal quality, the UM (UM1-UM5) selects its antenna and the best node antenna for use. An alternate antenna is selected if a person is determined to be present in a predetermined area adjacent a UM (UM1-UM5) corresponding to a predetermined RF power level.
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公开(公告)号：AU624745B2
公开(公告)日：1992-06-18
申请号：AU6524790
申请日：1990-08-23
Applicant: MOTOROLA INC
Inventor： WHITE RICHARD E , BUCHHOLZ DALE R , JOHANSON LISA B , FREEBURG THOMAS A
Abstract: A network interface architecture for a packet/fast packet switch is described. This architecture provides for the combination of both voice and data in a single switch using a common packet structure. It allows for the dynamic allocation of bandwidth based on system loading. This includes not only bandwidth within the voice or data areas of the frame, but also between the voice and data portions. The network interface (105) provides a means (101) of passing all packets through the Network Interface (105) or allowing the packet devices to directly transfer packets between one another. The bandwidth allocation can easily be changed because the control and data memories are synchronized to one another. The architecture allows for the data packets and the control of bandwidth allocation to be controlled by a single switching device. It synchronizes the transfer of the data and the allocation of bus bandwidth. The control of the packet devices can be controlled at a very high bit rate such as 40 Mbps. It allows packet devices to directly transfer packets. It allows for easy re-allocation of bandwidth through the use of the NI Base Registers.
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Patent Agency Ranking
公开(公告)号：BR9104906A
公开(公告)日：1992-04-14
申请号：BR9104906
申请日：1991-02-25
Applicant: MOTOROLA INC
Inventor： FREEBURG THOMAS A , WHITE RICHARD E
Abstract: An encryption circuit that operates with substantially zero delay. Using programmable keys and polynomials, the encryption algorithm can be constantly changed to thwart any unintended receiving parties from decoding the data. A key (101) and a polynomial (102) are loaded into registers. The key is then loaded into a shift register and shifted through XOR gates (106) at a programmable rate. The other input of the XOR gates come from the result of ANDing (103) a disable signal, the polynomial register (102), and the last stage of the shift register (104). Eight bits of the shift register outputs are XOR'ed with the input data to be encrypted. The output of these XOR gates (105) is the encrypted data.
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公开(公告)号：PT94530A
公开(公告)日：1992-02-28
申请号：PT9453090
申请日：1990-06-28
Applicant: MOTOROLA INC
Inventor： BERKEN JAMES J , MARX KENNETH J , THOMAS JAMES E , FREEBURG THOMAS A
Abstract: In a network of interconnected wireless networks (NODE, UIM) and wired telephone networks (PSTN, PBX), there is provided a mechanism for sustained association of users with communications paths. It is characterized by: upon an attempted use of an unassociated telephone, identifying oneself to the network (via the wireless network) and activating one's telephone line (pair 1, 2, 3 . . . n) by keying ones' own telephone number (12345, 12346 or 12347) through the telephone keypad, locating his telephone line (12345, 12346 or 12347) by monitoring unassociated lines (pair 1, 2, 3 . . . n) for activity, and the one so identified receiving a sustaining association (for more than a few communications) with the telephone line (pair 1, 2, 3 . . . n and UIM) so located.
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公开(公告)号：CS58191A3
公开(公告)日：1992-02-19
申请号：CS58191
申请日：1991-03-06
Applicant: MOTOROLA INC
Inventor： FREEBURG THOMAS A , WHITE RICHARD E
Abstract: An encryption circuit that operates with substantially zero delay. Using programmable keys and polynomials, the encryption algorithm can be constantly changed to thwart any unintended receiving parties from decoding the data. A key (101) and a polynomial (102) are loaded into registers. The key is then loaded into a shift register and shifted through XOR gates (106) at a programmable rate. The other input of the XOR gates come from the result of ANDing (103) a disable signal, the polynomial register (102), and the last stage of the shift register (104). Eight bits of the shift register outputs are XOR'ed with the input data to be encrypted. The output of these XOR gates (105) is the encrypted data.
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公开(公告)号：HUT58173A
公开(公告)日：1992-01-28
申请号：HU625890
申请日：1990-09-28
Applicant: MOTOROLA INC
Inventor： WHITE RICHARD E , BUCHHOLZ DALE R , JOHANSON LISA B , FREEBURG THOMAS A
Abstract: A network interface architecture for a packet/fast packet switch is described. This architecture provides for the combination of both voice and data in a single switch using a common packet structure. It allows for the dynamic allocation of bandwidth based on system loading. This includes not only bandwidth within the voice or data areas of the frame, but also between the voice and data portions. The network interface (105) provides a means (101) of passing all packets through the Network Interface (105) or allowing the packet devices to directly transfer packets between one another. The bandwidth allocation can easily be changed because the control and data memories are synchronized to one another. The architecture allows for the data packets and the control of bandwidth allocation to be controlled by a single switching device. It synchronizes the transfer of the data and the allocation of bus bandwidth. The control of the packet devices can be controlled at a very high bit rate such as 40 Mbps. It allows packet devices to directly transfer packets. It allows for easy re-allocation of bandwidth through the use of the NI Base Registers.
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公开(公告)号：HUT58172A
公开(公告)日：1992-01-28
申请号：HU649790
申请日：1990-10-18
Applicant: MOTOROLA INC
Inventor： NOLAN MICHAEL P , FREEBURG THOMAS A , CHANG HUNGKUN J , FARHANGNIA FARZAD
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