公开(公告)号：JP5319572B2

公开(公告)日：2013-10-16

申请号：JP2010036994

申请日：2010-02-23

Applicant: セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー

Inventor： 俊樹 ▲頼▼ ,  定男 吉川

IPC: G11C16/06 ,  G11C16/02 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: G11C7/1036 ,  G11C7/08

Abstract: With a serial interface memory device of this invention, a read-out rate of data is increased, while an increase in a size of a circuit is suppressed. An EEPROM is provided with a memory cell array storing data, a row address decoder and a column address decoder that select an address of the memory cell array in accordance with an address signal serially inputted in synchronization with a clock, sense amplifiers SA0-SA5, SA_M0 and SA_M1 each provided corresponding to each bit of the data, and a shift register that outputs the data read out from the sense amplifiers serially from a first bit. The column address decoder commences reading out two candidate data for the first bit by inputting each of the two candidate data to each of the two sense amplifiers SA_M0 and SA_M1, respectively, before all bits of the column address signal are established.

公开(公告)号：JP5213459B2

公开(公告)日：2013-06-19

申请号：JP2008001460

申请日：2008-01-08

Applicant: 三星電子株式会社Samsung Electronics Co.,Ltd.

Inventor： 龍雲 韓 ,  起岩 李

IPC: G11C29/12 ,  G11C11/413

CPC classification number: G11C29/44 ,  G11C7/1036 ,  G11C11/41 ,  G11C2029/2602

公开(公告)号：JP4808318B2

公开(公告)日：2011-11-02

申请号：JP2001004951

申请日：2001-01-12

Applicant: 三星電子株式会社Samsung Electronics Co.,Ltd.

Inventor： ケネス・ジェイ・エルドリッジ ,  フレデリック・エイ・パーナー

IPC: G11C19/00 ,  G11C7/10 ,  G11C19/28 ,  G11C29/12

CPC classification number: G11C7/1006 ,  G11C7/1036 ,  G11C19/00

公开(公告)号：JP4223712B2

公开(公告)日：2009-02-12

申请号：JP2001359844

申请日：2001-11-26

Applicant: 三星電子株式会社Samsung Electronics Co.,Ltd.

Inventor： 彰 植 康

IPC: G02F1/133 ,  G09G3/36 ,  G09G3/20 ,  G11C7/10 ,  G11C8/04

CPC classification number: G11C8/04 ,  G09G3/3688 ,  G11C7/1036

公开(公告)号：JP2004025833A

公开(公告)日：2004-01-29

申请号：JP2003049781

申请日：2003-02-26

Applicant: Lexmark Internatl Inc ,  レックスマーク・インターナショナル・インコーポレーテツドLexmark International,Inc

Inventor： GIBSON BRUCE DAVID ,  PARISH GEORGE KEITH

IPC: B41J2/01 ,  B41J2/045 ,  B41J2/05 ,  B41J2/055 ,  B41J2/125 ,  B41J2/175 ,  B41J25/34 ,  B41J29/38 ,  G11C7/10 ,  G11C8/10 ,  G11C16/02

CPC classification number: B41J2/17546 ,  B41J2/04541 ,  B41J2/04563 ,  B41J2/0458 ,  B41J2/17526 ,  B41J25/34 ,  B41J2202/17 ,  G11C7/1036 ,  G11C8/10

Abstract: PROBLEM TO BE SOLVED: To provide an inexpensive device, capable of increasing the amount of information stored in a printing head cartridge without increasing the number of address lines or complicating the printing head electronics.
SOLUTION: A memory device for storing and outputting information includes a plurality of memory matrices, each of which includes a plurality of transistors having a drain, a source and a gate, arranged in various levels from the minimum level to the maximum level. Furthermore, the device includes a plurality of single bit shift resistors for producing a consecutive output, and it has a memory input and a memory matrix related therewith. The memory input is connected electrically with the source of the transistor of the maximum level of the memory matrices. The memory device includes a plurality of address lines for receiving a decoding signal function, a loading signal, and a clock signal, and an outputting line for transmitting the consecutive output of the plurality of the shift resistors.
COPYRIGHT: (C)2004,JPO

公开(公告)号：EP3967497B1

公开(公告)日：2024-08-21

申请号：EP21198421.6

申请日：2019-02-06

IPC: B41J2/045 ,  G11C7/10 ,  G11C19/28

CPC classification number: G11C19/28 ,  G11C7/1015 ,  G11C7/103 ,  G11C7/1036 ,  G11C7/1033 ,  B41J2/0458 ,  B41J2/04551 ,  B41J2/04541 ,  B41J2/04521 ,  B41J2/04523

公开(公告)号：EP3803875B1

公开(公告)日：2024-07-24

申请号：EP19810423.4

申请日：2019-04-01

IPC: G11C16/34 ,  G11C11/22 ,  G11C7/10 ,  G11C13/00 ,  G11C16/08 ,  G11C16/24 ,  G06F12/02

CPC classification number: G11C16/3495 ,  G11C11/221 ,  G11C16/24 ,  G11C16/08 ,  G11C11/2255 ,  G11C11/2257 ,  G11C2207/223620130101 ,  G06F2212/721120130101 ,  G06F12/0246 ,  G11C7/1042 ,  G11C7/1039 ,  G11C7/1036 ,  G11C2207/227220130101 ,  G11C16/349 ,  G11C13/0035

公开(公告)号：EP3047485A4

公开(公告)日：2017-08-16

申请号：EP14846610

申请日：2014-08-28

Applicant: MICRON TECHNOLOGY INC

Inventor： COWLES TIMOTHY B ,  BODILY STEVEN M

IPC: G11C7/10 ,  G11C7/06

CPC classification number: G11C7/065 ,  G11C5/06 ,  G11C7/06 ,  G11C7/08 ,  G11C7/1006 ,  G11C7/1036 ,  G11C7/22 ,  G11C8/10 ,  G11C11/4091 ,  G11C19/00 ,  G11C2207/002 ,  G11C2207/005

Abstract: The present disclosure includes apparatuses and methods related to data shifting. An example apparatus comprises a first memory cell coupled to a first sense line of an array, a first isolation device located between the first memory cell and first sensing circuitry corresponding thereto, and a second isolation device located between the first memory cell and second sensing circuitry corresponding to a second sense line. The first and the second isolation devices are operated to shift data in the array without transferring the data via an input/output line of the array.

Abstract translation: 本公开包括与数据移位有关的设备和方法。 示例装置包括耦合到阵列的第一感测线的第一存储器单元，位于第一存储器单元和与其对应的第一感测电路之间的第一隔离器件以及位于第一存储器单元和第二感测电路之间的第二隔离器件 对应于第二感测线。 操作第一和第二隔离装置以移位阵列中的数据而不通过阵列的输入/输出线传送数据。

公开(公告)号：EP3014416A1

公开(公告)日：2016-05-04

申请号：EP14817022.8

申请日：2014-06-26

Applicant: Intel Corporation

Inventor： HINTON, Glenn ,  TOLL, Bret ,  SINGHAL, Ronak

IPC: G06F9/06 ,  G06F12/08

CPC classification number: G11C7/1036 ,  G06F9/30043 ,  G06F9/30109 ,  G06F9/30163

Abstract: A processor includes N-bit registers and a decode unit to receive a multiple register memory access instruction. The multiple register memory access instruction is to indicate a memory location and a register. The processor includes a memory access unit coupled with the decode unit and with the N-bit registers. The memory access unit is to perform a multiple register memory access operation in response to the multiple register memory access instruction. The operation is to involve N-bit data, in each of the N-bit registers comprising the indicated register. The operation is also to involve different corresponding N-bit portions of an MxN-bit line of memory corresponding to the indicated memory location. A total number of bits of the N-bit data in the N-bit registers to be involved in the multiple register memory access operation is to amount to at least half of the MxN-bits of the line of memory.

Abstract translation: 处理器包括N位寄存器和用于接收多寄存器存储器访问指令的解码单元。 多个寄存器存储器访问指令是指示存储器位置和寄存器。 处理器包括与解码单元和N位寄存器耦合的存储器存取单元。 存储器访问单元响应于多个寄存器存储器访问指令执行多个寄存器存储器访问操作。 该操作涉及在包括所指示的寄存器的每个N位寄存器中涉及N位数据。 操作还涉及对应于所指示的存储器位置的M×N位存储器线的不同对应的N位部分。 要在多个寄存器存储器存取操作中涉及的N位寄存器中的N位数据的总位数至少等于存储器行的M×N位的至少一半。

公开(公告)号：EP2737489A4

公开(公告)日：2015-03-11

申请号：EP12818284

申请日：2012-07-05

Applicant: MICRON TECHNOLOGY INC

Inventor： HENDRICKSON NICHOLAS

IPC: G11C16/34 ,  G11C7/10 ,  G11C11/56 ,  G11C16/04 ,  G11C16/26

CPC classification number: G11C16/26 ,  G11C7/1033 ,  G11C7/1036 ,  G11C7/1039 ,  G11C7/106 ,  G11C11/5642 ,  G11C16/0458 ,  G11C16/0483 ,  G11C2207/2272 ,  G11C2211/5642

Abstract: Apparatus and methods of operating memory devices are disclosed. In one such method, a first portion of the data states of memory cells are determined and transferred from a memory device while continuing to determine remaining portions of data states of the same memory cells. In at least one method, a data state of a memory cell is determined during a first sense phase and is transferred while the memory cell experiences additional sense phases to determine additional portions of the data state of the memory cell.