Abstract:
Systems for controlling the frequency of the output signal of a controllable oscillator (202) in a frequency synthesizer (200) are provided. One such system comprises a controllable oscillator (202) and a frequency control circuit (208). The controllable oscillator (202) is configured to generate an output signal that has a predefined frequency. The controllable oscillator (202) is also configured with a plurality of operational states that are controlled by the frequency control circuit. Each operational state of the controllable oscillator (202) defines a distinct frequency for the output signal of the controllable oscillator (202). The frequency control circuit receives the output signal of the controllable oscillator and determines the distinct frequency for the output signal that best approximates the predefined frequency. The frequency control circuit may also provide a control signal to the controllable oscillator that is configured to change the controllable oscillator to the operational state corresponding to the distinct frequency that best approximates the predefined frequency.
Abstract:
A programming method (250) for digitally programming the adjustment of an electronic trim capacitor (212, 314, 414). In an initial step (252), programming is initiated by setting an enable terminal (224). In subsequent steps (254, 256) a pulse signal (226) then applied to a program terminal (222) and the number of pulses (228) provided to the programming terminal (222) while the enable terminal (224) is set determines the total number of capacitance increments for which the electronic trim capacitor (212, 314, 414) is programmed. The electronic trim capacitor (212, 314, 414) may be incorporated into an integrated circuit (12, 312) or a module (412) and the electronic trim capacitor (212, 314, 414) may be programmed and used "in situ" in a more general circuit (1) such as an oscillator (301) or an amplifier (401).
Abstract:
A structure (110, 150) for enhancing the quality factor (Q) of a capacitive circuit (112, 152). The capacitive circuit (112, 152) includes a first resistance (122, 164), a capacitance (124, 166), and a second resistance (126, 168). The capacitance (124, 166) represents the net capacitance of the capacitive circuit (112, 152), and the first resistance (122, 164) and second resistance (126, 168) represent elements of the intrinsic resistance of the capacitive circuit (112, 152). In one embodiment the structure (110) includes a first capacitor (128) which is connected in parallel with the capacitive circuit (112), and second capacitor (130) which is connected in series with the capacitive circuit (112). In a second embodiment the structure (150) includes a first inductor (164), connected in series between the capacitive circuit (152) and a node (162) where the first capacitor (174) and one end of the second capacitor (176) connect, and a second inductor (172) connected in series between the capacitive circuit (152) and the other end of the second capacitor (130).
Abstract:
A frequency detector of a phase-lock-loop circuit is used for measuring a frequency error between a frequency of an output signal of an oscillator and a frequency of a synchronizing signal. When the frequency error in each of 32 periods of the synchronizing signal exceeds a predetermined magnitude, the phase-lock-loop circuits begins operating in a coarse frequency correction mode. As long as the 32 periods have not lapsed, the phase-lock-loop circuit operates in an idle mode of operation and the oscillator is not corrected. As a result, during vertical retrace, when equalizing pulses occur, the phase-lock-loop circuit is not disturbed by a large frequency error.
Abstract:
A frequency detector of a phase-lock-loop circuit is used for measuring a frequency error between a frequency of an output signal of an oscillator and a frequency of a synchronizing signal. When the frequency error in each of 32 periods of the synchronizing signal exceeds a predetermined magnitude, the phase-lock-loop circuits begins operating in a coarse frequency correction mode. As long as the 32 periods have not lapsed, the phase-lock-loop circuit operates in an idle mode of operation and the oscillator is not corrected. As a result, during vertical retrace, when equalizing pulses occur, the phase-lock-loop circuit is not disturbed by a large frequency error.
Abstract:
An oscillator includes a first VCXO and a second VCXO which are capable of changing an output frequency by application of a control voltage, and a control voltage terminal to which the control voltage is applied, the first VCXO includes a variable-capacitance diode (first variable-capacitance diode) and a resistor (first resistor), the second VCXO includes a variable-capacitance diode (second variable-capacitance diode) and a resistor (second resistor), the cutoff frequency of the first variable-capacitance diode, the second variable-capacitance diode, the first resistor, and the second resistor is equal to the cutoff frequency of the first variable-capacitance diode and the first resistor, and the cutoff frequency of the second variable-capacitance diode and the second resistor.
Abstract:
An electronic device includes an inductive element, and variable capacitors. Each variable capacitor includes: first and third capacitors, both having a first terminal electrically connected to a first terminal of the inductive element; and second and fourth capacitors, both having a first terminal electrically connected to a second terminal of the inductive element. A first switch circuit electrically connects or isolates a second terminal of the first capacitor to/from a second terminal of the second capacitor. A second switch circuit electrically connects or isolates a second terminal of the third capacitor to/from a second terminal of the fourth capacitor. A third switch circuit electrically connects or isolates the second terminal of the first capacitor to/from the second terminal of the fourth capacitor. A fourth switch circuit electrically connects or isolates the second terminal of the third capacitor to/from the second terminal of the second capacitor.
Abstract:
A transceiver for use in a wireless device. The transceiver may include a receive portion for receiving an input RF signal. The receive portion may include at least one receive filter which may include a first filter. The transceiver may also include a transmit portion for transmitting an output RF signal. The transmit portion may include at least one transmit filter, which may include the first filter used in the receive portion. The transceiver may further include a plurality of switches, which may include a first switch coupled to an input of the first filter and a second switch coupled to an output of the first filter. The plurality of switches may be configurable to enable use of the first filter in the receive portion for receiving the input RF signal and use of the first filter in the transmit portion for transmitting the output RF signal.
Abstract:
An inductor circuit includes a pair of inductors connected in parallel with each other and a switch for turning on and off electric power to one of the pair of inductors. The inductance of the inductor circuit can be varied and the quality factor Q can be improved. Further, RF circuits employing the inductor circuit can generate an intended operating frequency.
Abstract:
A gain compensator compensates for the gain variation of a varactor-tuned voltage tuned oscillator (VCO) in a phase lock loop (PLL). The VCO includes a parallel LC circuit having multiple fixed capacitors that can be switched-in or switched-out of the LC circuit according to a capacitor control signal to perform band-select tuning of the VCO. The gain compensator compensates for the variable VCO gain by generating a charge pump reference current that is based on the same capacitor control signal that controls the fixed capacitors in the LC circuit. The gain compensator generates the charge pump reference current by replicating a reference scale current using unit current sources. The number of times the reference scale current is replicated is based on the fixed capacitance that is switched-in to the LC circuit and therefore the frequency band of the PLL. The reference scale current is generated based on a PLL control that specifics certain PLL characteristics such as reference frequency, loop bandwidth, and loop damping. Therefore, the reference pump current can be efficiently optimized for-changing PLL operating conditions, in addition to compensating for variable VCO gain.