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201 records (took 0.027 seconds)

    Converter device
    151.
    发明公开
    Converter device 失效
    转换器

    公开(公告)号：EP0310170A3

    公开(公告)日：1990-05-23

    申请号：EP88202028.2

    申请日：1988-09-16

    Applicant: ALCATEL N.V. ,  BELL TELEPHONE MANUFACTURING COMPANY Naamloze Vennootschap

    Inventor： Haspeslagh, Didier René ,  Rabaey, Dirk Herman Lutgardis Cornelius

    IPC: H03K9/06

    CPC classification number: H03K9/08

    Abstract: Converter device for converting a PDM signal to an analog signal (OUT11/12). This device includes a main circuit comprising a conversion circuit (CC1) to which are supplied a PDM signal and control signals (CL1, CL2) which are dependent on supply voltages VDD and VSS, and an integrator circuit (LPF1). In a regulating circuit (CC2, LPF2, COMP2, PWM2) a reference signal (PDMR) is converted and integrated in the same way as the PDM signal and measurement signals (V21, V22) are generated which are function of the deviations of VDD and VSS from their normal value respectively. With these signals the respective control signals are compensated in such a manner that the converted signal (011/12) provided by the conversion circuit (CC1) becomes independent from these deviations.

    Electric converter
    154.
    发明公开
    Electric converter 失效
    电动转换器

    公开(公告)号：EP0316981A3

    公开(公告)日：1989-12-06

    申请号：EP88202416.9

    申请日：1988-10-29

    Applicant: ALCATEL N.V. ,  BELL TELEPHONE MANUFACTURING COMPANY Naamloze Vennootschap

    Inventor： Ryckebusch, Frank

    IPC: H02M3/335

    CPC classification number: H02M3/33507 ,  H02M3/33569 ,  H02M2001/0022

    Abstract: DC to DC voltage/current electric converter converting an input signal (V1) to an output signal (V2) and including an input circuit (IC) with a gating circuit (NM4) to apply the input signal thereat, an output circuit (OC) generating the output signal, and a converter circuit (PFM, PWM). The converter circuit includes a pulse generator (PFM, COMP3), generating a pulse stream (F5) having an average frequency which is function of the output signal, and a pulse width modulator circuit (PWM) which converts each pulse of the pulse stream into a pulse having a width (T2) which is function of the input signal (V1) and is used to control the gating circuit.

    Information transmission system
    156.
    发明公开
    Information transmission system 失效
    Nachrichtenübertragungssystem。

    公开(公告)号：EP0275129A2

    公开(公告)日：1988-07-20

    申请号：EP88200011.0

    申请日：1988-01-07

    Applicant: ALCATEL N.V. ,  BELL TELEPHONE MANUFACTURING COMPANY Naamloze Vennootschap

    Inventor： Verbiest, Willem Jules Antoine ,  Duponcheel, Marc Maurice Lucienne

    IPC: H04N11/04 ,  H04L1/02

    CPC classification number: H04L1/02 ,  H04N11/042 ,  H04N19/186 ,  H04N19/40 ,  H04N19/63

    Abstract: Information transmission system wherein information signals (Y1, C1; Y2, C2; Y3, C3) relating to a same video image and defining this image with a different accuracy are transmitted in an asynchronous way and on a time division basis under the form of packet sets (Y1, C1; Y21, C21; Y32, C32). In a receiving station (SS2) the information signals are derived from the received packet sets and by means of selection circuit (SEC1/3) two or more of these signals are supplied to a combination device (VTE) and are combined therein to form an image.

    Abstract translation: 信息传输系统，其中以相同视频图像定义与定义不同精度的图像的信息信号（Y1，C1; Y2，C2; Y3，C3）以异步方式并且以分组的形式以分组的形式被发送 （Y1，C1; Y21，C21; Y32，C32）。 在接收站（SS2）中，信息信号从接收到的分组集合中导出，并且通过选择电路（SEC1 / 3）将这些信号中的两个或更多个提供给组合设备（VTE），并将其组合在一起 图片。

    OPTICAL RECEIVER
    157.
    发明公开
    OPTICAL RECEIVER 失效
    光接收机。

    公开(公告)号：EP0216765A1

    公开(公告)日：1987-04-08

    申请号：EP85902026.0

    申请日：1985-04-18

    Applicant: BELL TELEPHONE MANUFACTURING COMPANY Naamloze Vennootschap

    Inventor： WITTERS, Hugo, Frans, Josef

    IPC: H03F3 ,  H04B10

    CPC classification number: H04B10/6911 ,  H03F3/082 ,  H04B10/69

    Abstract: Un récepteur optique avec un circuit de polarisation (T8, R2/3, R44/45) est adapté pour polariser inversement une photodiode (PIN). Ce circuit de polarisation pour des niveaux de puissance optique croissants déplace le point de fonctionnement de la photodiode (PIN) vers et dans la région de fonctionnement non linéaire de la photodiode qui devient alors polarisée vers l'avant et, pour des niveaux de puissance optique supérieurs à une valeur prédéterminée le circuit de polarisation fonctionne comme une source de courant constant qui envoie un courant constant (Ic) à ladite photodiode (PIN).

    Pulse corrector
    159.
    发明公开
    Pulse corrector 失效
    脉冲校正器

    公开(公告)号：EP0112599A3

    公开(公告)日：1986-03-19

    申请号：EP83201818

    申请日：1983-12-20

    Applicant: BELL TELEPHONE MANUFACTURING COMPANY Naamloze Vennootschap ,  International Standard Electric Corporation

    Inventor： Hoefman, Marc Edmond Maria

    IPC: H03L07/08 ,  H03K05/26

    CPC classification number: H03L7/089

    Abstract: Pulse corrector, for a phase locked loop, with first (R) and second (V) outputs coupled with a digital phase detector (DPD) and with first (T) and second (S) inputs coupled with a reference source and with the output of a controlled oscillator (VCO) respectively. After the end of an interruption of the reference source, at the first input there is generated a pulse (TL) whose first edge never leads the corresponding first edge at the second output and whose duration is not substantially smaller than the duration of a pulse (S4) at the second input.

    Signal processing arrangement
    160.
    发明公开
    Signal processing arrangement 失效
    Anordnung zur Signalverarbeitung。

    公开(公告)号：EP0167677A1

    公开(公告)日：1986-01-15

    申请号：EP84201049.8

    申请日：1984-07-13

    Applicant: BELL TELEPHONE MANUFACTURING COMPANY Naamloze Vennootschap ,  ALCATEL N.V.

    Inventor： Dierckx, Rudolf ,  Sallaerts, Daniel ,  Guebels, Pierre-Paul

    IPC: H04B3/23 ,  G06F15/336 ,  H03H21/00

    CPC classification number: H04B3/23 ,  H03H21/0012 ,  H03H2220/06 ,  H04B3/238

    Abstract: The signal processing arrangement is an adaptive digital filter comprising a digital filter coefficient updating circuit (CUC) which supplies updated filter coefficients to a digital filter circuit proper (FC) and is controlled by an error signal (E) derived from the output signal of the filter proper. Each of these two circuits (CUC, FC) is constituted by a systolic processor with a plurality of interconnected cells each able to calculates a function of the type mn + p in a bit serial way and in such a way that bits of a same rank are successively calculated in the cells starting from right to left.

    Abstract translation: 信号处理装置是一种自适应数字滤波器，包括一个数字滤波器系数更新电路（CUC），该数字滤波器系数更新电路（CUC）将更新的滤波器系数提供给数字滤波器电路（FC），并由一个由 过滤适当。 这两个电路（CUC，FC）中的每一个由具有多个互连的单元的收缩处理器构成，每个互连单元能够以串行方式计算类型mn + p的功能，并且以这样的方式使相同排的位 在从右到左的单元格中连续计算。

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