公开(公告)号：US20040193667A1

公开(公告)日：2004-09-30

申请号：US10743274

申请日：2003-12-22

Applicant: STMicroelectronics S.A.

Inventor： Denis Lehongre

IPC: G06F017/14

CPC classification number: G06F7/22 ,  G11B20/1426 ,  H03H17/0263 ,  H03M5/00 ,  H03M5/04 ,  H03M5/145 ,  H03M7/46

Abstract: Device for processing digital data and, more particularly, for reading out the maximum or minimum value of data belonging to a set of 2n codes in which a relation of order is established and in which each of said data has a rank R comprised between 0 and 2nnull1. The device includes a conversion circuit for each digital data to be processed, which circuit generates a transform which is a binary number composed of 2nnull1 binary elements Tnullxnull with xnull1 to 2nnull1Tnull2nnull1nullTnull2nnull2null . . . Tnullxnull . . . Tnull2nullTnull1nullin which T(x)null0 when x is strictly higher than R and T(x)null1 when x is lower or equal to R. The result of the conversions is received by circuits that carry out a digital processing thereof.

Abstract translation: 更具体地说，用于读出属于其中建立了顺序关系并且其中每个所述数据具有等级R的2 代码的集合的数据的最大值或最小值的装置 介于0和2 -1之间。 该装置包括用于要处理的每个数字数据的转换电路，该电路产生一个二进制数变换，该二进制数由x = 1至2 -1的2 -1个二进制元素T [x]组成 [2 -1] T [2n -2]。 。 。 T [x]。 。 。 当x低于或等于R时，当x严格高于R且T（x）= 1时，T [2] T [1]其中T（x）= 0。转换的结果由携带的电路 进行数字处理。

公开(公告)号：US20040174737A1

公开(公告)日：2004-09-09

申请号：US10729192

申请日：2003-12-05

Applicant: STMicroelectronics S.A.

Inventor： Philippe Graffouliere

IPC: G11C011/00

CPC classification number: G11B27/24 ,  G11B7/007 ,  G11B7/00745 ,  G11B20/10009 ,  G11B20/14 ,  G11B20/1403 ,  G11B20/18 ,  G11B27/3027 ,  G11B2220/218 ,  G11B2220/2545 ,  G11B2220/2562

Abstract: For indicating on a data medium (9) a sector referenced by a binary word (16) formed of a number M of first bytes each comprising a number L of bits, the method includes steps of etching onto the data medium locally at this sector a succession of M second bytes each corresponding to a first byte, each second byte being equal to a vector of N components, each with a value of null1 or null1, such that Nnull2Lnull1 and such that the scalar product of said vector with any other vector to which another second byte is equal, is at most equal to null1. The data medium (9) is, for example, an optical disk.

Abstract translation: 为了在数据介质（9）上指示由二进制字（16）引用的扇区，该二进制字由包括数字L位的M个第一字节组成，该方法包括以下步骤：在该扇区处本地蚀刻到数据介质上 每个对应于第一字节的M个第二字节的连续，每个第二个字节等于N个分量的向量，每个分量的值为+1或-1，使得N = 2L -1，并且使得标量 所述向量与另一个第二字节相等的任何其他向量的乘积最大等于+1。 数据媒体（9）例如是光盘。

公开(公告)号：US20040169566A1

公开(公告)日：2004-09-02

申请号：US10731978

申请日：2003-12-10

Applicant: STMicroelectronics S.A.

Inventor： Fabrice Guitton ,  Francois Dupont

IPC: H03H007/42

CPC classification number: H03H7/422 ,  H03H7/42

Abstract: A mode-switching transformer selective on a band centered on a first frequency, comprising, between a same common mode input/output terminal and respectively one of two differential mode input/output terminals, a high-pass filter with a cut-off frequency smaller than said first frequency, a band-pass filter with a central frequency greater than said first frequency.

Abstract translation: 一种在以第一频率为中心的频带上选择性的模式切换变压器，包括在相同的共模输入/输出端和两个差分模式输入/输出端之中的一个之间，具有截止频率较小的高通滤波器 具有比所述第一频率高的中心频率大于所述第一频率的带通滤波器。

公开(公告)号：US20040160311A1

公开(公告)日：2004-08-19

申请号：US10782550

申请日：2004-02-18

Applicant: STMicroelectronics S.A.

Inventor： William Orlando ,  Jean Nicolai

IPC: H03D003/24

CPC classification number: G06F21/725 ,  G06F21/10 ,  G06F2221/2135 ,  G06F2221/2137

Abstract: An electronic circuit comprising a first counter clocked by a clock signal provided to have a first period and provided by an oscillator external to the circuit, and comprising a second counter clocked with a second period by an oscillator internal to the circuit, the second counter being reset each time the content of the first counter is a multiple of a first predetermined value, and a means for activating an alert signal when the second counter reaches a second predetermined value such that the product of the second predetermined value by the second period is greater than the product of the first predetermined value by the first period.

Abstract translation: 一种电子电路，包括由提供为具有第一周期并由电路外部的振荡器提供的时钟信号时钟的第一计数器，并且包括由电路内部的振荡器以第二周期计时的第二计数器，第二计数器 每当第一计数器的内容是第一预定值的倍数时复位，以及用于当第二计数器达到第二预定值时激活警报信号的装置，使得第二预定值乘第二周期的乘积更大 比第一个预定值乘以第一个周期的乘积。

公开(公告)号：US20040160279A1

公开(公告)日：2004-08-19

申请号：US10675810

申请日：2003-09-30

Applicant: STMicroelectronics S.A.

Inventor： Philippe Jouen ,  Michael Kraemer

IPC: H03L007/00

CPC classification number: H03L7/18 ,  H03L7/0891 ,  H03L7/099

Abstract: A phase-locked loop including an oscillator, controlled by a control signal generated by a comparison circuit comparing a reference frequency and the oscillator frequency and filtered by an integrator low-pass filter; a control and adjustment circuit for, with a predetermined frequency smaller than the reference frequency, taking into account the value of the filtered controlled signal and, if this value is out of a range of predetermined values, adjusting the operating range of the oscillator; and an inhibition circuit for deactivating the comparison circuit for a predetermined duration before taking into account the value of the filtered control signal.

Abstract translation: 一种锁相环，包括由比较电路产生的控制信号控制的振荡器，比较电路比较参考频率和振荡器频率，并由积分器低通滤波器滤波; 考虑到滤波后的受控信号的值，并且如果该值在预定值的范围之外，则调整振荡器的工作范围，该控制和调整电路具有小于参考频率的预定频率。 以及抑制电路，用于在考虑滤波后的控制信号的值之前，将比较电路停止预定的持续时间。

公开(公告)号：US20040143420A1

公开(公告)日：2004-07-22

申请号：US10697792

申请日：2003-10-30

Applicant: STMicroelectronics S.A.

Inventor： Maurice Le Van Suu ,  Michel Romet

IPC: G06F015/00

CPC classification number: H02J13/0075 ,  Y02E60/7853 ,  Y04S40/126

Abstract: This invention relates to an energy management system in an energy distribution network (DSTR) comprising an energy source (SE1) and a number of energy consumers (K1, K2, K3) distributed in different consumption locations, this system comprising the installation of distributed energy operation means (RXE) and distributed information transmission means (RTI) in each consumption location, and installation of centralised distributed energy management means (CGED) and centralised information transmission means (CTI) in the network (DSTR), transmitting control signals (SC) to the distributed energy operation means (RXE) passing through the distributed information transmission means (RTI).

Abstract translation: 本发明涉及能量分配网络（DSTR）中的能量管理系统，该能量管理系统包括能量源（SE1）和分布在不同消耗位置的多个能量消耗器（K1，K2，K3），该系统包括安装分布式能量 在每个消费位置中的操作装置（RXE）和分布式信息传输装置（RTI），以及在网络（DSTR）中集中分布式能量管理装置（CGED）和集中式信息传输装置（CTI）的安装，发送控制信号（SC） 涉及通过分布式信息传输装置（RTI）的分布式能量操作装置（RXE）。

公开(公告)号：US20040114051A1

公开(公告)日：2004-06-17

申请号：US10666839

申请日：2003-09-19

Applicant: STMICROELECTRONICS S.A

Inventor： Christian Tournier

IPC: H04N005/45

CPC classification number: H04N21/43607 ,  H04N5/4401 ,  H04N5/45 ,  H04N7/163 ,  H04N21/4147 ,  H04N21/4181 ,  H04N21/4263 ,  H04N21/4316 ,  H04N21/4382 ,  H04N21/4405

Abstract: A routing device is provided for transporting digital data from demodulated digital television signals. The routing device includes a network that routes the digital data to demultiplexers via at least one decoding module. The network includes means for connecting to at least two independent demodulation channels, with each of the demodulation channels producing digital data from a demodulator. The network allows individual routing of the digital data from each of the demodulation channels to the demultiplexers via at least one decoding module. Also provided are a corresponding routing method and a host device that includes such a routing device. Exemplary applications of the routing device and method are a digital television receiver with an image incorporation (picture in picture) function, and a digital television combined with a recording device.

Abstract translation: 提供路由设备用于从解调的数字电视信号传输数字数据。 路由设备包括经由至少一个解码模块将数字数据路由到解复用器的网络。 该网络包括用于连接至少两个独立解调信道的装置，每个解调信道从解调器产生数字数据。 网络允许经由至少一个解码模块将数字数据从每个解调信道单独路由到解复用器。 还提供了相应的路由方法和包括这种路由设备的主机设备。 路由设备和方法的示例性应用是具有图像并入（画中画）功能的数字电视接收机和与记录设备组合的数字电视机。

公开(公告)号：US20040107230A1

公开(公告)日：2004-06-03

申请号：US10721655

申请日：2003-11-25

Applicant: STMicroelectronics S.A.

Inventor： Michel Bardouillet

IPC: G06F001/02

CPC classification number: G06F7/588 ,  H03K3/84

Abstract: A generator of random numbers by a flip-flop having a data input receiving a first signal at a first frequency comprised in a predetermined range and the instantaneous value of which is conditioned by a disturbing signal, and having a clock input receiving a second signal at a second predetermined frequency, smaller than the first one, said second signal passing through a delay element giving it a delay greater than or equal to the maximum period of the first signal.

Abstract translation: 一种由触发器产生的随机数的发生器，其具有数据输入，该数据输入以包含在预定范围内的第一频率接收第一信号，其瞬时值由干扰信号调节，并且具有接收第二信号的时钟输入 第二预定频率小于第一预定频率，所述第二信号通过延迟元件，给予其大于或等于第一信号的最大周期的延迟。

公开(公告)号：US20040101169A1

公开(公告)日：2004-05-27

申请号：US10717745

申请日：2003-11-20

Applicant: STMicroelectronics S.A.

Inventor： Christel-Loic Tisse ,  Laurent Plaza ,  Guillaume Petitjean

IPC: G06K009/00

CPC classification number: G06K9/00597

Abstract: A method and a system determine a score characteristic of the definition of a digital imageby cumulating the quadratic norm of horizontal and vertical gradients of luminance values of pixels of the image, the pixels being chosen at least according to a first maximum luminance threshold of other pixels in the concerned direction.

Abstract translation: 一种方法和系统通过累积图像的像素的亮度值的水平和垂直梯度的二次方程来确定数字图像的定义的分数特征，所述像素至少根据其他像素的第一最大亮度阈值来选择 在有关方向。

公开(公告)号：US20040073749A1

公开(公告)日：2004-04-15

申请号：US10270753

申请日：2002-10-15

Applicant: STMICROELECTRONICS, INC. ,  STMICROELECTRONICS, S.A.

Inventor： Sivagnanam Parthasarathy ,  Andrew Cofler ,  Lionel Chaverot

IPC: G06F012/00

CPC classification number: G06F9/381 ,  G06F9/30181 ,  G06F9/325 ,  G06F9/3875 ,  G06F12/0864 ,  G06F12/0877 ,  G06F2212/1028 ,  Y02D10/13

Abstract: For instruction clusters for which no significant performance penalty is incurred, such as execution of hardware loops, a processor automatically and dynamically switches to a pipelined two-cycle access to an associated associative cache rather than a single-cycle access. An access involving more than one cycle uses less power because only the hit way within the cache memory is accessed rather than all ways within the indexed cache line. To maintain performance, the single-cycle cache access is utilized in all remaining instructions. In addition, where instruction clusters within a hardware loop fit entirely within a pre-fetch buffer, the cache sub-system is idled for any remaining iterations of the hardware loop to further reduce power consumption.

Abstract translation: 对于不会产生显着性能损失（如执行硬件循环）的指令集，处理器自动和动态切换到流水线的两周期访问关联的关联高速缓存而不是单周期访问。 涉及多个周期的访问使用更少的功率，因为​​只有高速缓存中的命中方式被访问，而不是索引的高速缓存行内的所有方式。 为了保持性能，在所有剩余指令中使用单周期高速缓存访​​问。 此外，在硬件环路内的指令集合完全适合预取缓冲器的情况下，高速缓存子系统对于硬件循环的任何剩余迭代都是空闲的，以进一步降低功耗。