公开(公告)号：WO2007141811A3

公开(公告)日：2007-12-13

申请号：PCT/IT2006/000420

申请日：2006-06-06

Applicant: STMicroelectronics S.r.l. ,  FROSINI Andrea ,  FISCHETTI Alessandra

Inventor： FROSINI Andrea ,  FISCHETTI Alessandra

IPC: C12Q1/68

Abstract: A process for preparing a semiconductor substrate for biological analysis in an integrated device, the biological analysis comprising the steps of amplifying DNA and detecting amplified DNA in the same chamber, comprises the steps of a) forming a silicon dioxide surface on said semiconductor substrate b) treating said silicon dioxide surface with a silane; c) forming a silanized surface; d) grafting nucleic acid probes; e) treating said silanized surface with a deactivating agent and f) forming a deactivated substrate sequentially. Further the process can include the step of cleaning the silicon dioxide substrate before the step of treating said silicon dioxide surface with a silane and the step of reacting the terminal group of the silane with a cross-linker or alternatively the step of reacting the derivatized nucleic acid probes with a cross-linker, before the grafting step.

公开(公告)号：WO2007108017A1

公开(公告)日：2007-09-27

申请号：PCT/IT2006/000170

申请日：2006-03-20

Applicant: STMicroelectronics S.r.l. ,  ROLANDI, Paolo ,  CALLIGARO, Cristiano ,  PASCUCCI, Luigi

Inventor： ROLANDI, Paolo ,  CALLIGARO, Cristiano ,  PASCUCCI, Luigi

IPC: H01L29/78 ,  H01L27/06 ,  H01L27/115 ,  H01L27/12 ,  H01L21/822

CPC classification number: H01L27/11551 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/1203 ,  H01L29/7832

Abstract: Semiconductor device (1; 38, 48) formed by a first conductive strip (10) of semiconductor material; a control gate region (7; 35; 55) of semiconductor material, facing a channel portion (5c) of the first conductive strip,- and an insulation region (6; 32; 52) arranged between the first conductive strip and the control gate region. The first conductive strip (10) includes a conduction line (5) having a first conductivity type and a control line (4) having a second conductivity type, arranged adjacent and in electrical contact with each other, and the conduction line (5) forms the channel portion (5c) , a first conduction portion (5a) and a second conduction portion (5b) arranged on opposite sides of the channel portion.

Abstract translation: 由半导体材料的第一导电条（10）形成的半导体器件（1; 38,48） 面对第一导电带的沟道部分（5c）的半导体材料的控制栅极区域（7; 35; 55）以及布置在第一导电带和控制栅极之间的绝缘区域（6; 32; 52） 地区。 第一导电条（10）包括具有第一导电类型的导线（5）和具有第二导电类型的控制线（4），彼此相邻并且彼此电接触，导线（5）形成 通道部分（5c），布置在通道部分的相对侧上的第一导电部分（5a）和第二导电部分（5b）。

公开(公告)号：WO2007096920A1

公开(公告)日：2007-08-30

申请号：PCT/IT2006/000117

申请日：2006-02-27

Applicant: STMICROELECTRONICS S.r.l. ,  CESURA, Giovanni Antonio ,  MASSOLINI, Roberto Giampiero

Inventor： CESURA, Giovanni Antonio ,  MASSOLINI, Roberto Giampiero

IPC: H03M1/10 ,  H03M1/40 ,  H03M1/44 ,  H03M1/16

CPC classification number: H03M1/1061 ,  H03M1/1004 ,  H03M1/162 ,  H03M1/164 ,  H03M1/40 ,  H03M1/44

Abstract: Multistage ADC (1) for converting in multi- step cycles, analogue samples (V] n) of an input signal (VIn) into digital codes (Dout) each cycle resolving at least one bit of digital code (Dout), the converter (1) including: - a generation block (3) of a pseudorandom sequence (Y' ts) to be summed to said analogue samples, obtaining a second sequence ( V+in) of analog samples; - conversion means (5) with controllable digital gain ( g ), receiving the second sequence (V+in) and outputting bits of said digital codes (Dout); - a feedback loop (2, 6, 7, 8) for performing said multi- step conversion cycles, with a loop gain (GLoop); - a digital calibration block (9) matching the digital gain ( g ) to the loop gain ( GLoop ); said second sequence (V+in) including predetermined samples with no contribution of said pseudorandom sequence (γ-ts); - a prediction block (10) to produce a digital estimation (Dout) of said input signal (Vin).

Abstract translation: 多级ADC（1）用于将多个输入信号（VIn）的多步循环的模拟样本（V] n）转换为数字代码（Dout），每个周期分解至少一位数字代码（Dout），转换器 1）包括： - 要与所述模拟样本求和的伪随机序列（Y'ts）的生成块（3），获得模拟样本的第二序列（V + in）; - 具有可控数字增益（g）的转换装置（5），接收第二序列（V + in）并输出所述数字码（Dout）的位; - 用于通过循环增益（GLoop）执行所述多级转换循环的反馈回路（2,6,7,8）; - 将数字增益（g）与环路增益（GLoop）匹配的数字校准块（9）; 所述第二序列（V + in）包括没有所述伪随机序列（α-ts）的贡献的预定样本; - 产生所述输入信号（Vin）的数字估计（Dout）的预测块（10）。

公开(公告)号：WO2007032032A1

公开(公告)日：2007-03-22

申请号：PCT/IT2005/000529

申请日：2005-09-16

Applicant: STMICROELECTRONICS S.R.L. ,  MURARI, Bruno ,  RICOTTI, Giulio ,  DELLA TORRE, Luigi ,  VITALI, Andrea, Lorenzo

Inventor： MURARI, Bruno ,  RICOTTI, Giulio ,  DELLA TORRE, Luigi ,  VITALI, Andrea, Lorenzo

IPC: G01L1/02 ,  G01L9/00

CPC classification number: G01L9/0054 ,  G01L1/02 ,  G01L5/225 ,  G01L9/0045 ,  G01L9/0089 ,  G01L19/0645 ,  G01L19/146

Abstract: In a pressure sensor (35) , a pressure-sensor element (10) has a monolithic body (12) of semiconductor material, and a first main face (12a) and a second main face (12b) acting on which is a stress resulting from a pressure (P) the value of which is to be determined; and a package (36) encloses the pressure­sensor element (10) . The package (36) has an inner chamber (37) containing liquid material (38), and the -ores sure-sensor element (10) is arranged within the inner chamber (37) in such a manner that the first and second main faces (12a, 12b) are both in contact with the liquid material (38). In particular, the liquid material is a silicone gel.

Abstract translation: 在压力传感器（35）中，压力传感器元件（10）具有半导体材料的整体（12），并且作用于其上的应力产生的第一主面（12a）和第二主面（12b） 从压力（P）来确定其值; 并且包装（36）包围所述压力传感器元件（10）。 包装（36）具有容纳液体材料（38）的内部室（37），并且 - 确定传感器元件（10）以这样的方式设置在内部室（37）内，使得第一和第二主要面 （12a，12b）都与液体材料（38）接触。 特别地，液体材料是硅胶。

公开(公告)号：WO2007031536A1

公开(公告)日：2007-03-22

申请号：PCT/EP2006/066316

申请日：2006-09-13

Applicant: STMICROELECTRONICS S.R.L. ,  KARPOV, Ilya ,  KIM, Yudong ,  JIN, Ming ,  TEEGAPURAM, Shyam Prasad ,  LEE, Jinwook

Inventor： KARPOV, Ilya ,  KIM, Yudong ,  JIN, Ming ,  TEEGAPURAM, Shyam Prasad ,  LEE, Jinwook

IPC: H01L27/24

CPC classification number: H01L45/16 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126

Abstract: A phase change memory formed by a plurality of phase change memory devices having a chalcogenide memory region (28) extending over an own heater (26). The heaters (26) have all a relatively uniform height. The height uniformity is achieved by forming the heaters within pores in an insulator that includes an etch stop layer (18) and a sacrificial layer (24). The sacrificial layer is removed through an etching process such as chemical mechanical planarization. Since the etch stop layer may be formed in a repeatable way and is common across all the devices on a wafer, considerable uniformity is achieved in heater height. Heater height uniformity results in more uniformity in programmed memory characteristics.

Abstract translation: 一种由具有在自身加热器（26）上延伸的硫族化物存储区域（28）的多个相变存储器件形成的相变存储器。 加热器（26）具有相对均匀的高度。 通过在包括蚀刻停止层（18）和牺牲层（24）的绝缘体的孔内形成加热器来实现高度均匀性。 通过诸如化学机械平面化的蚀刻工艺去除牺牲层。 由于蚀刻停止层可以以可重复的方式形成，并且在晶片上的所有器件上是共同的，所以在加热器高度方面实现了相当大的均匀性。 加热器高度均匀性导致编程存储器特性更均匀。

公开(公告)号：WO2007010574A1

公开(公告)日：2007-01-25

申请号：PCT/IT2005/000435

申请日：2005-07-22

Applicant: STMICROELECTRONICS S.R.L. ,  RICOTTI, Giulio ,  MORELLI, Marco ,  DELLA TORRE, Luigi ,  VITALI, Andrea, Lorenzo

Inventor： RICOTTI, Giulio ,  MORELLI, Marco ,  DELLA TORRE, Luigi ,  VITALI, Andrea, Lorenzo

IPC: G01L1/18 ,  G01L9/00 ,  G01L9/06

CPC classification number: G01L1/18 ,  B60T2270/82

Abstract: In an integrated pressure sensor (15) with a high full-scale value, a monolithic body (16) of semiconductor material has a first and a second main surface (16a and 16b), opposite and separated by a substantially uniform distance (w). The monolithic body (16) has a bulk region (17), having a sensitive portion (23) next to the first main surface (16a), upon which pressure (P) acts. A first piezoresistive detection element (18) is integrated in the sensitive portion (23) and has a variable resistance as a function of the pressure (P). The bulk region (17) is a solid and compact region and has a thickness substantially equal to the distance (w).

Abstract translation: 在具有高满量程值的集成压力传感器（15）中，半导体材料的整体（16）具有第一和第二主表面（16a和16b），所述第一和第二主表面相对并分开大致均匀的距离（w） 。 整体式主体（16）具有主体区域（17），其具有靠近第一主表面（16a）的敏感部分（23），压力（P）作用在该区域上。 第一压阻检测元件（18）集成在敏感部分（23）中并且具有作为压力（P）的函数的可变电阻。 本体区域（17）是实心且紧凑的区域，其厚度基本上等于距离（w）。

公开(公告)号：WO2007006505A1

公开(公告)日：2007-01-18

申请号：PCT/EP2006/006673

申请日：2006-07-07

Applicant: STMICROELECTRONICS S.R.L. ,  SAGGIO, Mario, Giuseppe ,  FRISINA, Ferruccio ,  RASCUNA, Simone

Inventor： SAGGIO, Mario, Giuseppe ,  FRISINA, Ferruccio ,  RASCUNA, Simone

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/7802 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/66712

Abstract: Process for manufacturing a multi-drain power electronic device (30) integrated on a semiconductor substrate (100) of a first type of conductivity whereon a drain semiconductor layer (20) is formed, characterised in that it comprises the following steps: forming at least a first semiconductor epitaxial layer (21) of the first type of conductivity forming the drain epitaxial layer (20) on the semiconductor substrate (100) , forming first sub-regions (51) of a second type of conductivity by means of a first selective implant step forming second sub-regions (Dl, DIa) of the first type of conductivity by means of a second implant step forming a surface semiconductor layer (23) wherein body regions (40) of the second type of conductivity are formed being aligned with the first sub-regions (51) , carrying out a thermal diffusion process so that the first sub-regions (51) form a single electrically continuous column region (50) being aligned and in electric contact with the body regions (40).

Abstract translation: 一种集成在形成有漏极半导体层（20）的第一导电类型的半导体衬底（100）上的多漏极功率电子器件（30）的制造方法，其特征在于包括以下步骤：至少形成 在所述半导体衬底（100）上形成所述漏极外延层（20）的所述第一导电类型的第一半导体外延层（21），通过第一选择性形成第二导电类型的第一子区域（51） 植入步骤通过形成表面半导体层（23）的第二注入步骤形成第一类型导电性的第二子区域（D1，DIa），其中形成第二导电类型的主体区域（40）与 所述第一子区域（51）进行热扩散处理，使得所述第一子区域（51）形成与所述主体区域（40）电接触的单个电连续列区域（50）。

公开(公告)号：WO2007006502A1

公开(公告)日：2007-01-18

申请号：PCT/EP2006/006670

申请日：2006-07-07

Applicant: STMICROELECTRONICS S.R.L. ,  RONSISVALLE, Cesare ,  ENEA, Vincenzo

Inventor： RONSISVALLE, Cesare ,  ENEA, Vincenzo

IPC: H01L29/78 ,  H01L27/07

CPC classification number: H01L29/7803 ,  H01L27/0259 ,  H01L27/0716 ,  H01L29/7302 ,  H01L29/739 ,  H01L29/7808 ,  H01L29/866

Abstract: A power actuator (20) of the emitter-switched type is described, the power actuator comprising at least one high voltage bipolar transistor (2) and a low voltage DMOS transistor (3) connected in cascode configuration between a collector terminal (C) of the bipolar transistor (2) and a source terminal (S) of the DMOS transistor (3) and having respective control terminals (B, G). Advantageously according to the invention, the power actuator (20) further comprises at least a Zener diode (21), inserted between the source terminal (S) of the DMOS transistor (3) and the control terminal (B) of the bipolar transistor (2).

Abstract translation: 描述了发射器切换型的电源致动器（20），功率致动器包括至少一个高压双极晶体管（2）和低电压DMOS晶体管（3），其以共源共栅结构连接在集电极端子（C）之间 双极晶体管（2）和DMOS晶体管（3）的源极端子（S）并具有各自的控制端子（B，G）。 有利地，根据本发明，功率致动器（20）还包括至少一个齐纳二极管（21），其插入在DMOS晶体管（3）的源极端（S）和双极晶体管的控制端（B）之间 2）。

公开(公告)号：WO2006103247A1

公开(公告)日：2006-10-05

申请号：PCT/EP2006/061118

申请日：2006-03-28

Applicant: STMICROELECTRONICS S.R.L. ,  PRANDI, Luciano ,  LASALANDRA, Ernesto ,  UNGARETTI, Tommaso

Inventor： PRANDI, Luciano ,  LASALANDRA, Ernesto ,  UNGARETTI, Tommaso

IPC: H03H9/02

CPC classification number: H03H9/02409 ,  G01C19/5726 ,  G01P15/097 ,  G01P15/125 ,  G01P2015/0814 ,  H03H2009/02496

Abstract: A device for controlling the frequency of resonance of an oscillating micro-electromechanical system includes: a microstructure (2), having a first body (10) and a second body (11) , which is capacitively coupled to the first body (10) and elastically oscillatable with respect thereto at a calibratable frequency of resonance (ω R ) , a relative displacement (ΔY) between the second body (11) and the first body (10) being detectable from outside; and an amplifier (21) coupled to the microstructure (2) for detecting the relative displacement (ΔY) . DC decoupling elements (23) are arranged between the amplifier (21) and the microstructure (2).

Abstract translation: 用于控制振荡微机电系统的共振频率的装置包括：具有电容耦合到第一主体（10）的第一主体（10）和第二主体（11）的微结构（2）和 以可校准的共振频率弹性振荡，第二体（11）和第一体（10）之间的相对位移（ΔY）可从外部检测; 以及耦合到微结构（2）的用于检测相对位移（ΔY）的放大器（21）。 DC去耦元件（23）布置在放大器（21）和微结构（2）之间。

公开(公告)号：WO2005117402A1

公开(公告)日：2005-12-08

申请号：PCT/IT2005/000281

申请日：2005-05-19

Applicant: STMICROELECTRONICS S.R.L. ,  NICOLLINI, Germano ,  CONFALONIERI, Pierangelo ,  MARTIGNONE, Riccardo

Inventor： NICOLLINI, Germano ,  CONFALONIERI, Pierangelo ,  MARTIGNONE, Riccardo

IPC: H04M1/74

CPC classification number: H04B1/707

Abstract: There is described a circuit for reconstructing an analog signal from a digital signal and wide-band transmission system, particularly for employment in cellular telephony systems, or more in general in mobile communication systems, that adopt the WCDMA standard. The circuit comprises: a digital to analog converter (DAC) suitable for receiving said digital signal and converting it into signal in analog.format; - a low pass-filter (LOW-PASS) connected at the output of said converter for receiving said signal in analog format and providing as output said reconstructed analog signal. Advantageously, the low pass filter (LOW-PASS) is an active filter continuous in time and current­ coupled to the output of the digital-analog converter (DAC) and the digital-analog converter (DAC) is a converter of the current-steering type functioning at sampling frequency greater than the Nyquist frequency of said analog signal to be reconstructed.

Abstract translation: 描述了一种用于从数字信号和宽带传输系统重建模拟信号的电路，特别是用于蜂窝电话系统中的用途，或更一般地在采用WCDMA标准的移动通信系统中。 该电路包括：适于接收所述数字信号并将其转换为模拟信号的数模转换器（DAC）; - 低通滤波器（LOW-PASS），连接在所述转换器的输出端，用于以模拟格式接收所述信号，并提供所述重构模拟信号的输出。 有利地，低通滤波器（LOW-PASS）是连续的数字模拟转换器（DAC）的输出端的时间和电流连续的有源滤波器，并且数模转换器（DAC）是电流转向器 在大于待重构的所述模拟信号的奈奎斯特频率的采样频率下工作。