公开(公告)号：EP1876524B1

公开(公告)日：2011-10-12

申请号：EP07111351.8

申请日：1996-08-16

Applicant: MicroUnity Systems Engineering, Inc.

Inventor： Hansen, Craig c/o MicroUnity, Inc. ,  Moussouris, John c/o MicroUnity, Inc.

IPC: G06F9/30 ,  G06F15/76

CPC classification number: G06F9/3802 ,  G06F9/30 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/30145 ,  G06F9/3867 ,  G06F9/3869 ,  G06F12/0875 ,  G06F12/1027 ,  G06F15/7832 ,  G06F15/7842 ,  G06F2212/2515 ,  H04N21/2365 ,  H04N21/238 ,  H04N21/23805 ,  H04N21/4347 ,  Y02D10/13

Abstract: A general purpose, programmable media processor (12) for processing and transmitting a media data streams. The media processor (12) incorporates an execution unit (100) that maintains substantially peak data through out of media data streams. The execution unit (100) includes a dynamically partionable multi-precision arithmetic unit (102), programmable switch (104) and programmable extended mathematical element (106). A high bandwidth external interface (124) supplies media data streams at substantially peak rates to a general purpose register file (110) and the execution unit. A memory management unit, and instruction and data cache/buffers (118, 120) are provided. The general purpose, programmable media processor (12) is disposed in a network fabric consisting of fiber optic cable, coaxial cable and twisted pair wires to transmit, process and receive single or unified media data streams.

公开(公告)号：EP1879398A3

公开(公告)日：2008-12-10

申请号：EP07112548.8

申请日：1996-08-16

Applicant: MicroUnity Systems Engineering, Inc.

Inventor： Hansen, Craig ,  Moussouris, John

IPC: G06F9/30 ,  G06F15/76

CPC classification number: G06F9/3802 ,  G06F9/30 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/30145 ,  G06F9/3867 ,  G06F9/3869 ,  G06F12/0875 ,  G06F12/1027 ,  G06F15/7832 ,  G06F15/7842 ,  G06F2212/2515 ,  H04N21/2365 ,  H04N21/238 ,  H04N21/23805 ,  H04N21/4347 ,  Y02D10/13

Abstract: A set-top box for processing streams of media data which comprise a combination of at least two of audio, video, radio, graphics, encryption, authentication, and networking information. The set-top box processes streams of media data and has at least one programmable media processor (12) for receiving, processing and transmitting the stream of media data over the bi-directional communications network. The processor executes group instructions to read a plurality of data elements of the media data stream from a register file (110), to perform, on the data elements, group operations including both group integer and group floating point operations capable of dynamically partitioning the data by each specifying one of a plurality of data element sizes, and to write concatenated results in the register file.

Abstract translation: 用于处理媒体数据流的机顶盒，其包括音频，视频，无线电，图形，加密，认证和联网信息中的至少两种的组合。 机顶盒处理媒体数据流，并具有至少一个用于通过双向通信网络接收，处理和传输媒体数据流的可编程媒体处理器（12）。 处理器执行组指令以从寄存器文件（110）读取媒体数据流的多个数据元素，以对数据元素执行包括能够动态分区数据的组整数和组浮点操作的组操作 每个指定多个数据元素大小中的一个，并将连接结果写入寄存器文件。

公开(公告)号：EP1879104A3

公开(公告)日：2008-08-13

申请号：EP07112553.8

申请日：1996-08-16

Applicant: MicroUnity Systems Engineering, Inc.

Inventor： Hansen, Craig ,  Moussouris, John

IPC: G06F9/30 ,  G06F15/76

CPC classification number: G06F9/3802 ,  G06F9/30 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/30145 ,  G06F9/3867 ,  G06F9/3869 ,  G06F12/0875 ,  G06F12/1027 ,  G06F15/7832 ,  G06F15/7842 ,  G06F2212/2515 ,  H04N21/2365 ,  H04N21/238 ,  H04N21/23805 ,  H04N21/4347 ,  Y02D10/13

Abstract: A communication network capable of for processing streams of media data which comprise a combination of at least two of audio, video, radio, graphics, encryption, authentication, and networking information. The communications network processes streams of media data and has at least one programmable media processor (12) for receiving, processing and transmitting the stream of media data over the bi-directional communications network. The processor executes group instructions to read a plurality of data elements of the media data stream from a register file (100), to perform, on the data elements, group operations including both group integer and group floating point operations capable of dynamically partitioning the data by each specifing one of a plurality of data element sizes, and to write concatenated results in the register file. Each media processor (12) is reprogrammable by receiving downloaded software over the network.

公开(公告)号：EP1873629A3

公开(公告)日：2008-07-30

申请号：EP07111348.4

申请日：1996-08-16

Applicant: MicroUnity Systems Engineering, Inc.

Inventor： Hansen, Craig c/o MicroUnity Inc. ,  Moussouris, John c/o MicroUnity Inc.

IPC: G06F9/30 ,  G06F15/76

CPC classification number: G06F9/3802 ,  G06F9/30 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/30145 ,  G06F9/3867 ,  G06F9/3869 ,  G06F12/0875 ,  G06F12/1027 ,  G06F15/7832 ,  G06F15/7842 ,  G06F2212/2515 ,  H04N21/2365 ,  H04N21/238 ,  H04N21/23805 ,  H04N21/4347 ,  Y02D10/13

Abstract: A general purpose, programmable media processor (12) for processing and transmitting a media data streams. The media processor (12) incorporates an execution unit (100) that maintains substantially peak data through out of media data streams. The execution unit (100) includes a dynamically partionable multi-precision arithmetic unit (102), programmable switch (104) and programmable extended mathematical element (106). A high bandwidth external interface (124) supplies media data streams at substantially peak rates to a general purpose register file (110) and the execution unit. A memory management unit, and instruction and data cache/buffers (118, 120) are provided. The general purpose, programmable media processor (12) is disposed in a network fabric consisting of fiber optic cable, coaxial cable and twisted pair wires to transmit, process and receive single or unified media data streams.

公开(公告)号：EP1873630A3

公开(公告)日：2008-05-28

申请号：EP07111352.6

申请日：1996-08-16

Applicant: MicroUnity Systems Engineering, Inc.

Inventor： Hansen, Craig ,  Moussouris, John

IPC: G06F9/30 ,  G06F15/76

CPC classification number: G06F9/3802 ,  G06F9/30 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/30145 ,  G06F9/3867 ,  G06F9/3869 ,  G06F12/0875 ,  G06F12/1027 ,  G06F15/7832 ,  G06F15/7842 ,  G06F2212/2515 ,  H04N21/2365 ,  H04N21/238 ,  H04N21/23805 ,  H04N21/4347 ,  Y02D10/13

Abstract: A general purpose, programmable media processor (12) for processing and transmitting a media data streams. The media processor (12) incorporates an execution unit (100) that maintains substantially peak data through out of media data streams. The execution unit (100) includes a dynamically partionable multi-precision arithmetic unit (102), programmable switch (104) and programmable extended mathematical element (106). A high bandwidth external interface (124) supplies media data streams at substantially peak rates to a general purpose register file (110) and the execution unit. A memory management unit, and instruction and data cache/buffers (118, 120) are provided. The general purpose, programmable media processor (12) is disposed in a network fabric consisting of fiber optic cable, coaxial cable and twisted pair wires to transmit, process and receive single or unified media data streams.

公开(公告)号：EP1876524A3

公开(公告)日：2008-03-19

申请号：EP07111351.8

申请日：1996-08-16

Applicant: MicroUnity Systems Engineering, Inc.

Inventor： Hansen, Craig c/o MicroUnity, Inc. ,  Moussouris, John c/o MicroUnity, Inc.

IPC: G06F9/30 ,  G06F15/76

CPC classification number: G06F9/3802 ,  G06F9/30 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/30145 ,  G06F9/3867 ,  G06F9/3869 ,  G06F12/0875 ,  G06F12/1027 ,  G06F15/7832 ,  G06F15/7842 ,  G06F2212/2515 ,  H04N21/2365 ,  H04N21/238 ,  H04N21/23805 ,  H04N21/4347 ,  Y02D10/13

Abstract: A general purpose, programmable media processor (12) for processing and transmitting a media data streams. The media processor (12) incorporates an execution unit (100) that maintains substantially peak data through out of media data streams. The execution unit (100) includes a dynamically partionable multi-precision arithmetic unit (102), programmable switch (104) and programmable extended mathematical element (106). A high bandwidth external interface (124) supplies media data streams at substantially peak rates to a general purpose register file (110) and the execution unit. A memory management unit, and instruction and data cache/buffers (118, 120) are provided. The general purpose, programmable media processor (12) is disposed in a network fabric consisting of fiber optic cable, coaxial cable and twisted pair wires to transmit, process and receive single or unified media data streams.

公开(公告)号：EP1879397A2

公开(公告)日：2008-01-16

申请号：EP07111480.5

申请日：1996-08-16

Applicant: MicroUnity Systems Engineering, Inc.

Inventor： Hansen, Craig c/o MicroUnity, Inc. ,  Moussouris, John c/o MicroUnity, Inc.

IPC: H04N7/24 ,  G06F15/76

CPC classification number: G06F9/3802 ,  G06F9/30 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/30145 ,  G06F9/3867 ,  G06F9/3869 ,  G06F12/0875 ,  G06F12/1027 ,  G06F15/7832 ,  G06F15/7842 ,  G06F2212/2515 ,  H04N21/2365 ,  H04N21/238 ,  H04N21/23805 ,  H04N21/4347 ,  Y02D10/13

Abstract: A general purpose, programmable media processor (12) for processing and transmitting a media data streams. The media processor (12) incorporates an execution unit (100) that maintains substantially peak data through out of media data streams. The execution unit (100) includes a dynamically partionable multi-precision arithmetic unit (102), programmable switch (104) and programmable extended mathematical element (106). A high bandwidth external interface (124) supplies media data streams at substantially peak rates to a general purpose register file (110) and the execution unit. A memory management unit, and instruction and data cache/buffers (118, 120) are provided. The general purpose, programmable media processor (12) is disposed in a network fabric consisting of fiber optic cable, coaxial cable and twisted pair wires to transmit, process and receive single or unified media data streams.

公开(公告)号：EP1876524A2

公开(公告)日：2008-01-09

申请号：EP07111351.8

申请日：1996-08-16

Applicant: MicroUnity Systems Engineering, Inc.

Inventor： Hansen, Craig c/o MicroUnity, Inc. ,  Moussouris, John c/o MicroUnity, Inc.

IPC: G06F9/30 ,  G06F15/76

CPC classification number: G06F9/3802 ,  G06F9/30 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/30145 ,  G06F9/3867 ,  G06F9/3869 ,  G06F12/0875 ,  G06F12/1027 ,  G06F15/7832 ,  G06F15/7842 ,  G06F2212/2515 ,  H04N21/2365 ,  H04N21/238 ,  H04N21/23805 ,  H04N21/4347 ,  Y02D10/13

Abstract: A general purpose, programmable media processor (12) for processing and transmitting a media data streams. The media processor (12) incorporates an execution unit (100) that maintains substantially peak data through out of media data streams. The execution unit (100) includes a dynamically partionable multi-precision arithmetic unit (102), programmable switch (104) and programmable extended mathematical element (106). A high bandwidth external interface (124) supplies media data streams at substantially peak rates to a general purpose register file (110) and the execution unit. A memory management unit, and instruction and data cache/buffers (118, 120) are provided. The general purpose, programmable media processor (12) is disposed in a network fabric consisting of fiber optic cable, coaxial cable and twisted pair wires to transmit, process and receive single or unified media data streams.

Abstract translation: 一种用于处理和发送媒体数据流的通用可编程媒体处理器（12）。 媒体处理器（12）包括执行单元（100），其通过媒体数据流保持基本上峰值数据。 执行单元（100）包括动态分离多精度运算单元（102），可编程开关（104）和可编程扩展数学元件（106）。 高带宽外部接口（124）以基本上峰值的速率将媒体数据流提供给通用寄存器文件（110）和执行单元。 提供存储器管理单元，以及指令和数据高速缓冲存储器/缓冲器（118,120）。 通用的可编程媒体处理器（12）被布置在由光纤电缆，同轴电缆和双绞线组成的网络结构中，以传输，处理和接收单个或统一的媒体数据流。

公开(公告)号：EP1554692A2

公开(公告)日：2005-07-20

申请号：EP03776530.2

申请日：2003-10-24

Applicant: Complex Systems Engineering, Inc.

Inventor： JACEK, Marczyk

IPC: G06N7/02

CPC classification number: G06N7/02 ,  G06F17/5009 ,  G06F2217/10

Abstract: A process for the computer creation of fuzzy cognitive maps (see Fig. 7) that are used to explore causal relationships (302) between a group of factors and a phenomenon. These fuzzy cognitive maps are constructed using the data derived from Expanded Meta Models (25). These Expanded Meta Models are generated from Monte Carlo simulations that supply the factors under investigation with values, then by incrementing or decrementing these factor values one can generated an Expanded Meta Model (25).

公开(公告)号：EP1236090A1

公开(公告)日：2002-09-04

申请号：EP00910150.2

申请日：2000-02-11

Applicant: Microunity Systems Engineering, Inc.

Inventor： HANSEN, Craig ,  BATEMAN, Bruce ,  MOUSSOURIS, John

IPC: G06F9/30

CPC classification number: G06F7/76 ,  G06F9/30018

Abstract: The present invention provides a cross-bar circuit (100) that implements a switch (115) of a broadband processor. The cross-bar circuit (100) includes: a switch circuit (115) which includes 2m.2n:1 multiplexor circuits (202-204) where each of the 2n:1 multiplexor circuits (202-204) has a unique n-bit index input, one disable input, and a 2n-bit wide source input receives an n-bit index at the n-bit index input, a disable bit at the disable input, and the 2n-bit input source word at the 2n-bit wide source input, and decodes the n-bit index either to select and output as an output destination bit one bit from the 2n-bit input source word if the disable bit has a logic low value; a cache memory (110) that has 2m cache datapath inputs; and 2m cache index input; and a control circuit (105) that has a plurality of control inputs receives the partially decoded instruction information on the plurality of control inputs, provides a second set of the n-bit indexes for the switch circuit (115), and provides the disable bits for the switch circuit (115) where the control circuit (105) is logically coupled to the switch circuit (115) and to the cache memory (110).