公开(公告)号：NO891583A

公开(公告)日：1989-11-27

申请号：NO891583

申请日：1989-04-18

Applicant: IBM

Inventor： BEGUN RALPH MURRAY ,  BLAND PATRICK MAURICE ,  DEAN MARK EDWARD

IPC: G06F12/08 ,  G06F12/06 ,  G06F13/38

CPC classification number: G06F12/0802

公开(公告)号：NO891581L

公开(公告)日：1989-11-27

申请号：NO891581

申请日：1989-04-18

Applicant: IBM

Inventor： BLAND PATRICK MAURICE ,  DEAN MARK EDWARD

IPC: G06F13/36 ,  G06F13/362 ,  G11C11/401 ,  G11C7/10 ,  G06F12/06 ,  G06F13/10

Abstract: A computer system includes a page memory in which a row address accompanied by a row address strobe (RAS) is followed by a column address accompanied by a column address strobe (CAS) to read data from a memory location during a memory cycle. When, in a following memory cycle, a further location from the same page is to be accessed, the row address and the RAS remain constant and a new column address is used with the CAS being precharged by switching it to its OFF state and then returning it to its ON state. This is normally done at the start of the following memory cycle. In the present system, the data is read and latched shortly after arrival of the column address and CAS in the first of the memory cycles so that the CAS recharge can take place at the end of the first memory cycle and before the start of the following memory cycle.

公开(公告)号：AT43194T

公开(公告)日：1989-06-15

申请号：AT84115242

申请日：1984-12-14

Applicant: IBM

Inventor： DEAN MARK EDWARD

IPC: G06F12/00 ,  G11C11/24 ,  G11C11/406

Abstract: A refresh generator system (5) for a dynamic memory (3) in a data processing system, including a processor (1) which is responsive to a hold request signal (HRQ) to relinquish control of the local bus and generate a hold acknowledge signal (HLDA), comprises logic means (14,11.10,13) to generate a hold request signal in response to an output from a refresh timer circuit (6). A logic circuit (16) is responsive to a hold request, a corresponding hold acknowledge, and the timer signal to generate a refresh control signal (REFR). This signal generates a refresh signal for the memory control circuits, increments a counter circuit (19) and initiates operation of a sequencer circuit (22). The sequencer then gates the output of the counter circuit to provide a memory row address and thereafter provides a memory read output (-MEMR) to refresh the memory row defined by the address and lastly resets the circuit to terminate the hold request signal.

公开(公告)号：IT8920649D0

公开(公告)日：1989-05-25

申请号：IT2064989

申请日：1989-05-25

Applicant: IBM

Inventor： BEGUN RALPH MURRAY ,  BLAND PATRICK MAURICE ,  DEAN MARK EDWARD

IPC: G06F12/08

Abstract: In a dual bus microcomputer system using a cache memory and a cache controller, the timing requirements placed on non-cache memory components by the cache controller are more stringent than the timing requirements placed on the non-cache memory components by the microprocessor. A logic circuit operates on the cache write enable (CWE) signals, and delays those signals in the event of a cache read miss. Delaying the CWE signals relaxes the timing requirements placed on non-cache memory components and at the same time does not impact wait state parameters for read miss operations.

公开(公告)号：IT8920624D0

公开(公告)日：1989-05-24

申请号：IT2062489

申请日：1989-05-24

Applicant: IBM

Inventor： BLAND PATRICK MAURICE ,  DEAN MARK EDWARD

IPC: G11C11/401 ,  G06F13/36 ,  G06F13/362 ,  G11C7/10

Abstract: A computer system includes a page memory in which a row address accompanied by a row address strobe (RAS) is followed by a column address accompanied by a column address strobe (CAS) to read data from a memory location during a memory cycle. When, in a following memory cycle, a further location from the same page is to be accessed, the row address and the RAS remain constant and a new column address is used with the CAS being precharged by switching it to its OFF state and then returning it to its ON state. This is normally done at the start of the following memory cycle. In the present system, the data is read and latched shortly after arrival of the column address and CAS in the first of the memory cycles so that the CAS recharge can take place at the end of the first memory cycle and before the start of the following memory cycle.

公开(公告)号：DK189589D0

公开(公告)日：1989-04-19

申请号：DK189589

申请日：1989-04-19

Applicant: IBM

Inventor： BLAND PATRICK MAURICE ,  DEAN MARK EDWARD

IPC: G11C11/401 ,  G06F13/36 ,  G06F13/362 ,  G11C7/10 ,  G06F12/00 ,  G06F13/00

Abstract: A computer system includes a page memory in which a row address accompanied by a row address strobe (RAS) is followed by a column address accompanied by a column address strobe (CAS) to read data from a memory location during a memory cycle. When, in a following memory cycle, a further location from the same page is to be accessed, the row address and the RAS remain constant and a new column address is used with the CAS being precharged by switching it to its OFF state and then returning it to its ON state. This is normally done at the start of the following memory cycle. In the present system, the data is read and latched shortly after arrival of the column address and CAS in the first of the memory cycles so that the CAS recharge can take place at the end of the first memory cycle and before the start of the following memory cycle.

公开(公告)号：DK189489D0

公开(公告)日：1989-04-19

申请号：DK189489

申请日：1989-04-19

Applicant: IBM

Inventor： BEGUN RALPH MURRAY ,  BLAND PATRICK MAURICE ,  DEAN MARK EDWARD

IPC: G06F9/38 ,  G06F12/08 ,  G06F12/00 ,  G06F13/00

Abstract: In a microcomputer system comprising a microprocessor and a cache subsystem and operable in a pipelined mode, there is potential incompatibility between pipelined operations and dynamic bus sizing as the cache subsystem operates with a fixed size data width and dynamic bus sizing allows the system to operate with devices of differing data width. This incompatibility is accommodated by the present system by defining certain addresses as cacheable addresses and other addresses as non-cacheable addresses and ensuring that addresses of devices of data width different from the cache data width are non-cacheable. An address decoder provides a control signal indicating whether or not a generated address is within the cacheable range. This control signal controls a next address signal applied to the microprocessor, which signal allows the processor to proceed to a following cycle prior to the end of the current cycle. Whenever a non-cacheable address is detected, the next address signal is suppressed.

公开(公告)号：NO891583D0

公开(公告)日：1989-04-18

申请号：NO891583

申请日：1989-04-18

Applicant: IBM

Inventor： BEGUN RALPH MURRAY ,  BLAND PATRICK MAURICE ,  DEAN MARK EDWARD

IPC: G06F12/08 ,  G06F

Abstract: In a dual bus microcomputer system using a cache memory and a cache controller, the timing requirements placed on non-cache memory components by the cache controller are more stringent than the timing requirements placed on the non-cache memory components by the microprocessor. A logic circuit operates on the cache write enable (CWE) signals, and delays those signals in the event of a cache read miss. Delaying the CWE signals relaxes the timing requirements placed on non-cache memory components and at the same time does not impact wait state parameters for read miss operations.

公开(公告)号：NO891581D0

公开(公告)日：1989-04-18

申请号：NO891581

申请日：1989-04-18

Applicant: IBM

Inventor： BLAND PATRICK MAURICE ,  DEAN MARK EDWARD

IPC: G06F13/36 ,  G11C11/401 ,  G06F13/362 ,  G11C7/10 ,  G06F

Abstract: A computer system includes a page memory in which a row address accompanied by a row address strobe (RAS) is followed by a column address accompanied by a column address strobe (CAS) to read data from a memory location during a memory cycle. When, in a following memory cycle, a further location from the same page is to be accessed, the row address and the RAS remain constant and a new column address is used with the CAS being precharged by switching it to its OFF state and then returning it to its ON state. This is normally done at the start of the following memory cycle. In the present system, the data is read and latched shortly after arrival of the column address and CAS in the first of the memory cycles so that the CAS recharge can take place at the end of the first memory cycle and before the start of the following memory cycle.

公开(公告)号：FI891787A0

公开(公告)日：1989-04-14

申请号：FI891787

申请日：1989-04-14

Applicant: IBM

Inventor： BEGUN RALPH MURRAY ,  DEAN MARK EDWARD ,  BLAND PATRICK MAURICE

IPC: G06F9/38 ,  G06F12/08 ,  G06F

Abstract: In a microcomputer system comprising a microprocessor and a cache subsystem and operable in a pipelined mode, there is potential incompatibility between pipelined operations and dynamic bus sizing as the cache subsystem operates with a fixed size data width and dynamic bus sizing allows the system to operate with devices of differing data width. This incompatibility is accommodated by the present system by defining certain addresses as cacheable addresses and other addresses as non-cacheable addresses and ensuring that addresses of devices of data width different from the cache data width are non-cacheable. An address decoder provides a control signal indicating whether or not a generated address is within the cacheable range. This control signal controls a next address signal applied to the microprocessor, which signal allows the processor to proceed to a following cycle prior to the end of the current cycle. Whenever a non-cacheable address is detected, the next address signal is suppressed.