-
公开(公告)号：US20180300933A1
公开(公告)日：2018-10-18
申请号：US15489177
申请日：2017-04-17
Applicant: Intel Corporation
Inventor： Devan Burke , Adam T. Lake , Jeffery S. Boles , John H. Feit , Karthik Vaidyanathan , Abhishek R. Appu , Joydeep Ray , Subramaniam Maiyuran , Altug Koker , Balaji Vembu , Murali Ramadoss , Prasoonkumar Surti , Eric J. Hoekstra , Gabor Liktor , Jonathan Kennedy , Slawomir Grajewski , Elmoustapha Ould-Ahmed-Vall
IPC: G06T15/00
Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, and a graphics subsystem communicatively coupled to the application processor. The system may include one or more of a draw call re-orderer communicatively coupled to the application processor and the graphics subsystem to re-order two or more draw calls, a workload re-orderer communicatively coupled to the application processor and the graphics subsystem to re-order two or more work items in an order independent mode, a queue primitive included in at least one of the two or more draw calls to define a producer stage and a consumer stage, and an order-independent executor communicatively coupled to the application processor and the graphics subsystem to provide tile-based order independent execution of a compute stage. Other embodiments are disclosed and claimed.
-
公开(公告)号：US20180300905A1
公开(公告)日：2018-10-18
申请号：US15488801
申请日：2017-04-17
Applicant: Intel Corporation
Inventor： Robert J. Johnston , Abhishek R. Appu , Stanley J. Baran , Sang-Hee Lee , Atthar H. Mohammed , Jong Dae Oh , Hiu-Fai R. Chan , Joydeep Ray
IPC: G06T9/00 , H04N19/136 , G06T15/00
Abstract: Image information is often transmitted from one electronic device to another. Such information is typically encoded and/or compressed to reduce the bandwidth required for transmission and/or to decrease the time necessary for transmission. Embodiments are directed to tagging objects or primitives with attribute tags to facilitate the encoding process. Other embodiments are directed to codecs running on hardware and/or software.
-
公开(公告)号：US20180300847A1
公开(公告)日：2018-10-18
申请号：US15489015
申请日：2017-04-17
Applicant: Intel Corporation
Inventor： Balaji Vembu , Josh B. Mastronarde , Altug Koker , Nikos Kaburlasos , Abhishek R. Appu , Joydeep Ray
Abstract: Methods and apparatus relating to techniques for power management. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to receive one or more frames for a workload, determine one or more compute resource parameters for the workload, and store the one or more compute resource parameters for the workload in a memory in association with workload context data for the workload. Other embodiments are also disclosed and claimed.
-
公开(公告)号：US20180300177A1
公开(公告)日：2018-10-18
申请号：US15489062
申请日：2017-04-17
Applicant: Intel Corporation
Inventor： Altug Koker , Abhishek R. Appu , Kiran C. Veernapu , Joydeep Ray , Balaji Vembu
Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to receive a completion acknowledgment from the plurality of graphics processing units and in response to a determination that the workload is finished, to terminate one or more communication connections on the interconnect bridge. Other embodiments are also disclosed and claimed.
-
公开(公告)号：US10102149B1
公开(公告)日：2018-10-16
申请号：US15488840
申请日：2017-04-17
Applicant: Intel Corporation
Inventor： Abhishek R. Appu , Joydeep Ray , James A. Valerio , Altug Koker , Prasoonkumar P. Surti , Balaji Vembu , Wenyin Fu , Bhushan M. Borole , Kamal Sinha
IPC: G06F12/12 , G06F12/128 , G06F12/0811 , G06F13/40 , G06T1/20
Abstract: A hybrid hierarchical cache is implemented at the same level in the access pipeline, to get the faster access behavior of a smaller cache and, at the same time, a higher hit rate at lower power for a larger cache, in some embodiments. A split cache at the same level in the access pipeline includes two caches that work together. In the hybrid, split, low level cache (e.g., L1) evictions are coordinated locally between the two L1 portions, and on a miss to both L1 portions, a line is allocated from a larger L2 cache to the smallest L1 cache.
-
Patent Agency Ranking
公开(公告)号：US20180293702A1
公开(公告)日：2018-10-11
申请号：US15483059
申请日：2017-04-10
Applicant: Intel Corporation
Inventor： Abhishek R. Appu , Joydeep Ray , Altug Koker , Balaji Vembu , Prasoonkumar P. Surti , Kamal Sinha , Vasanth Ranganathan , Kiran C. Veernapu , Bhushan M. Borole , Wenyin Fu
CPC classification number: G06T1/60 , G06T1/20 , G06T15/005
Abstract: In accordance with one embodiment each page table entry maps a variable page size (per entry), if multiple continuous virtual pages map to contiguous physical pages. This may drastically reduce the number of translation lookaside buffer (TLB) entries needed since each entry can potentially map a larger chunk of memory, in some embodiments.
-
公开(公告)号：US20180293697A1
公开(公告)日：2018-10-11
申请号：US15483623
申请日：2017-04-10
Applicant: Intel Corporation
Inventor： Joydeep Ray , Ankur N. Shah , Abhishek R. Appu , Deepak S. Vembar , ElMoustapha Ould-Ahmed-Vall , Atsuo Kuwahara , Travis T. Schluessler , Linda L. Hurd , Josh B. Mastronarde , Vasanth Ranganathan
CPC classification number: G06T1/20 , G06F9/30145 , G06F9/3851 , G06F9/3887 , G06T15/005
Abstract: An embodiment of a graphics apparatus may include a context engine to determine contextual information, a recommendation engine communicatively coupled to the context engine to determine a recommendation based on the contextual information, and a configuration engine communicatively coupled to the recommendation engine to adjust a configuration of a graphics operation based on the recommendation. Other embodiments are disclosed and claimed.
-
公开(公告)号：US20180293205A1
公开(公告)日：2018-10-11
申请号：US15482796
申请日：2017-04-09
Applicant: Intel Corporation
Inventor： Altug Koker , Farshad Akhbari , Feng Chen , Dukhwan Kim , Narayan Srinivasa , Nadathur Rajagopalan Satish , Liwei Ma , Jeremy Bottleson , Eriko Nurvitadhi , Joydeep Ray , Ping T. Tang , Michael Strickland , Xiaoming Chen , Tatiana Shpeisman , Abhishek R. Appu
CPC classification number: G06F15/8007 , G06F9/3004 , G06F13/00 , G06F13/4027 , G06N3/0445 , G06N3/0454 , G06N3/0481 , G06N3/063 , G06N3/084 , G06T1/20
Abstract: An integrated circuit (IC) package apparatus is disclosed. The IC package includes one or more processing units and a bridge, mounted below the one or more processing unit, including one or more arithmetic logic units (ALUs) to perform atomic operations.
-
公开(公告)号：US20180293173A1
公开(公告)日：2018-10-11
申请号：US15483741
申请日：2017-04-10
Applicant: Intel Corporation
Inventor： Jianfang Zhu , Cristiano J. Ferreira , Bo Qiu , Ajit Krisshna Nandyal Lakshman , Nikhil Talpallikar , Deepak Gandiga Shivakumar , Brandt M. Guttridge , Kim Pallister , Frank J. Soqui , Anand Srivatsa , Travis T. Schluessler , Abhishek R. Appu , Ankur N. Shah , Joydeep Ray , Altug Koker , Jonathan Kennedy
IPC: G06F12/10
Abstract: An embodiment of an electronic processing system may include an application processor, system memory communicatively coupled to the application processor, a graphics processor communicatively coupled to the application processor, graphics memory communicatively coupled to the graphics processor, and persistent storage media communicatively coupled to the application processor and the graphics processor to store one or more graphics assets, wherein the graphics processor is to access the one or more graphics asset mapped from the persistent storage media. The persistent storage media may include a low latency, high capacity, and byte-addressable nonvolatile memory. The one or more graphics assets may include one or more of a mega-texture and terrain data. Other embodiments are disclosed and claimed.
-
公开(公告)号：US20180293170A1
公开(公告)日：2018-10-11
申请号：US15483001
申请日：2017-04-10
Applicant: Intel Corporation
Inventor： Altug Koker , Joydeep Ray , James A. Valerio , Abhishek R. Appu , Vasanth Ranganathan
IPC: G06F12/0842
CPC classification number: G06F12/0842 , G06F2212/1008 , G06F2212/455
Abstract: A mechanism is described for facilitating independent and separate entity-based graphics cache at computing devices. A method of embodiments, as described herein, includes facilitate hosting of a plurality of cache at a plurality of entities associated with a graphics processor, wherein each entity hosts at least one cache, and wherein an entity includes a dual sub-slice (DSS) or a streaming multiprocessor (SM).
-
-
-
-
-
-
-
-
-
Search Results
868
records
(took 0.06 seconds)
