公开(公告)号：US11430751B2

公开(公告)日：2022-08-30

申请号：US16465132

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Georgios C. Dogiamis ,  Telesphor Kamgaing ,  Sasha N. Oster

IPC: H01L23/66 ,  H01L23/31 ,  H01L23/538 ,  H01L23/552 ,  H01L25/16 ,  H01Q1/22 ,  H01Q1/24 ,  H01Q1/52

Abstract: Embodiments of the invention include a microelectronic device that includes a first ultra thin substrate formed of organic dielectric material and conductive layers, a first mold material to integrate first radio frequency (RF) components with the first substrate, and a second ultra thin substrate being coupled to the first ultra thin substrate. The second ultra thin substrate formed of organic dielectric material and conductive layers. A second mold material integrates second radio frequency (RF) components with the second substrate.

公开(公告)号：US20220199546A1

公开(公告)日：2022-06-23

申请号：US17127382

申请日：2020-12-18

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Gerald S. Pasdast ,  Kimin Jun ,  Zhiguo Qian ,  Johanna M. Swan ,  Aleksandar Aleksov ,  Shawna M. Liff ,  Mohammad Enamul Kabir ,  Feras Eid ,  Kevin P. O'Brien ,  Han Wui Then

IPC: H01L23/552 ,  H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  H01L23/66

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first microelectronic component, having a first surface and an opposing second surface including a first direct bonding region at the second surface with first metal contacts and a first dielectric material between adjacent ones of the first metal contacts; a second microelectronic component, having a first surface and an opposing second surface, including a second direct bonding region at the first surface with second metal contacts and a second dielectric material between adjacent ones of the second metal contacts, wherein the second microelectronic component is coupled to the first microelectronic component by the first and second direct bonding regions; and a shield structure in the first direct bonding dielectric material at least partially surrounding the one or more of the first metal contacts.

公开(公告)号：US20220199450A1

公开(公告)日：2022-06-23

申请号：US17132429

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Shawna M. Liff ,  Johanna M. Swan ,  Adel A. Elsherbini ,  Michael J. Baker ,  Aleksandar Aleksov ,  Feras Eid

IPC: H01L21/683 ,  H01L23/00 ,  H01L21/67

Abstract: Described herein are carrier assemblies, and related devices and methods. In some embodiments, a carrier assembly includes a carrier; a textured material including texturized microstructures coupled to the carrier; and microelectronic components mechanically coupled to the texturized microstructures. In some embodiments, a carrier assembly includes a carrier having a front side and a back side; an electrode on the front side of the carrier; a dielectric material on the electrode; a charging contact on the back side coupled to the electrode; and microelectronic components electrostatically coupled to the front side of the carrier. In some embodiments, a carrier assembly includes a carrier having a front side and a back side; electrodes on the front side; a dielectric material including texturized microstructures on the electrodes; charging contacts on the back side coupled to the plurality of electrodes; and microelectronic components mechanically and electrostatically coupled to the front side of the carrier.

公开(公告)号：US11360512B2

公开(公告)日：2022-06-14

申请号：US16567479

申请日：2019-09-11

Applicant: Intel Corporation

Inventor： Nadine L. Dabby ,  Sasha N. Oster ,  Aleksandar Aleksov ,  Braxton Lathrop ,  Racquel L Fygenson

IPC: H05K3/30 ,  G06F1/16 ,  H05K3/34 ,  H05K3/32 ,  H05K1/03 ,  H05K1/02 ,  H05K3/28

Abstract: Systems and methods describe herein provide a solution to the technical problem of creating a wearable electronic devices. In particular, these systems and methods enable electrical and mechanical attachment of stretchable or flexible electronics to fabric. A stretchable or flexible electronic platform is bonded to fabric using a double-sided fabric adhesive, and conductive adhesive is used to join pads on the electronic platform to corresponding electrical leads on the fabric. An additional waterproofing material may be used over and beneath the electronic platform to provide a water-resistant or waterproof device This stretchable or flexible electronic platform integration process allows the platform to bend and move with the fabric while protecting the conductive connections. By using flexible and stretchable conductive leads and adhesives, the platform is more flexible and stretchable than traditional rigid electronics enclosures.

公开(公告)号：US11329358B2

公开(公告)日：2022-05-10

申请号：US16841072

申请日：2020-04-06

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Mathew Manusharow ,  Krishna Bharath ,  Zhichao Zhang ,  Yidnekachew S. Mekonnen ,  Aleksandar Aleksov ,  Henning Braunisch ,  Feras Eid ,  Javier Soto

IPC: H01P3/08 ,  H01P3/02 ,  H05K1/02 ,  H01P3/06

Abstract: Embodiments of the invention include a packaged device with transmission lines that have an extended thickness, and methods of making such device. According to an embodiment, the packaged device may include a first dielectric layer and a first transmission line formed over the first dielectric layer. Embodiments may then include a second dielectric layer formed over the transmission line and the first dielectric layer. According to an embodiment, a first line via may be formed through the second dielectric layer and electrically coupled to the first transmission line. In some embodiments, the first line via extends substantially along the length of the first transmission line.

公开(公告)号：US11328996B2

公开(公告)日：2022-05-10

申请号：US16648640

申请日：2017-12-30

Applicant: Intel Corporation

Inventor： Veronica Strong ,  Aleksandar Aleksov ,  Brandon Rawlings

IPC: H01L23/538 ,  H01L23/522 ,  H01L23/00

Abstract: A device package and method of forming the device package are described. The device package includes a dielectric on a conductive pad, a first via on a top surface of conductive pad, where the first via extends through dielectric, and a conductive trace on dielectric. The device package has a second via on dielectric, where the conductive trace connects to first and second vias, and the second via connects to an edge of conductive trace opposite from first via. The device package may have a seed on dielectric, where the seed electrically couples to conductive trace, a first seed on the top surface of conductive pad, where the first via is on first seed, and a second seed on a top surface of first via, the second seed on surfaces of second via, where the conductive trace is on second seed disposed on both first and second vias.

公开(公告)号：US11310907B2

公开(公告)日：2022-04-19

申请号：US16697699

申请日：2019-11-27

Applicant: Intel Corporation

Inventor： Georgios Dogiamis ,  Aleksandar Aleksov ,  Feras Eid ,  Telesphor Kamgaing ,  Johanna M. Swan

IPC: H05K1/02 ,  H05K1/16 ,  H05K3/12 ,  H05K3/40 ,  H05K9/00

Abstract: Embodiments may relate to a microelectronic package or a die thereof which includes a die, logic, or subsystem coupled with a face of the substrate. An inductor may be positioned in the substrate. Electromagnetic interference (EMI) shield elements may be positioned within the substrate and surrounding the inductor. Other embodiments may be described or claimed.

公开(公告)号：US11309192B2

公开(公告)日：2022-04-19

申请号：US16000205

申请日：2018-06-05

Applicant: Intel Corporation

Inventor： Kristof Kuwawi Darmawikarta ,  Robert May ,  Sri Ranga Sai Boyapati ,  Srinivas V. Pietambaram ,  Chung Kwang Christopher Tan ,  Aleksandar Aleksov

IPC: H01L21/48 ,  H01L23/498

Abstract: Disclosed herein are integrated circuit (IC) package supports and related apparatuses and methods. For example, in some embodiments, an IC package support may include a non-photoimageable dielectric, and a conductive via through the non-photoimageable dielectric, wherein the conductive via has a diameter that is less than 20 microns. Other embodiments are also disclosed.

公开(公告)号：US20220093547A1

公开(公告)日：2022-03-24

申请号：US17025843

申请日：2020-09-18

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Zhiguo Qian ,  Gerald S. Pasdast ,  Mohammad Enamul Kabir ,  Han Wui Then ,  Kimin Jun ,  Kevin P. O'Brien ,  Johanna M. Swan ,  Shawna M. Liff ,  Aleksandar Aleksov ,  Feras Eid

IPC: H01L23/00 ,  H01L25/065 ,  H01L49/02

Abstract: Disclosed herein are microelectronic assemblies including microelectronic components that are coupled together by direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes at least part of an inductor.

公开(公告)号：US20220093520A1

公开(公告)日：2022-03-24

申请号：US17026703

申请日：2020-09-21

Applicant: Intel Corporation

Inventor： Jeremy D. Ecton ,  Aleksandar Aleksov ,  Brandon C. Marin ,  Yonggang Li ,  Leonel Arana ,  Suddhasattwa Nad ,  Haobo Chen ,  Tarek Ibrahim

IPC: H01L23/538 ,  H05K1/11 ,  H01L21/768

Abstract: Conductive routes for an electronic substrate may be fabricated by forming an opening in a material, using existing laser drilling or lithography tools and materials, followed by selectively plating a metal on the sidewalls of the opening. The processes of the present description may result in significantly higher patterning resolution or feature scaling (up to 2× improvement in patterning density/resolution). In addition to improved patterning resolution, the embodiments of the present description may also result in higher aspect ratios of the conductive routes, which can result in improved signaling, reduced latency, and improved yield.