Self-learning method and system for detecting abnormalities
    151.
    发明公开
    Self-learning method and system for detecting abnormalities 有权
    自学习的错误检测方法和系统

    公开(公告)号:EP1480126A3

    公开(公告)日:2007-08-22

    申请号:EP04008594.6

    申请日:2004-04-08

    Abstract: The present invention is directed to a method and system for use in a computing environment to monitor parameters and detect abnormalities. A monitoring system for monitoring a process may include a signature creation module (22) for creating a signature representative of the process, a signature updating module (24) for continuously updating the created signature, and an abnormality detection module (26) for detecting abnormalities based upon deviations from the updated signature. The system may perform a method for detecting abnormalities occurring during a process based upon the continuously updated signature representative of the process. The method may include continuously monitoring a system parameter and computing a normal range of values for the system parameter based on the continuously updated signature. The method may additionally include determining if the monitored system parameter is within the normal range and indicating existence of an abnormality if the monitored system parameter is outside of the normal range.

    Built-in self-test network
    152.
    发明授权
    Built-in self-test network 失效
    随着网络内建自测试

    公开(公告)号:EP0568239B1

    公开(公告)日:2001-07-25

    申请号:EP93303024.9

    申请日:1993-04-20

    Applicant: AT&T Corp.

    CPC classification number: G01R31/318536 G01R31/318533 G06F2201/83

    Abstract: Control of the self-testing of a plurality of elements (121 - 12m), each having a Built-In, Self-Test (BIST) capability, and arranged in one or more groups (141 - 14n), is carried out by a network (16) of one or more standard BIST resource interface controllers (SBRICs 181 - 18n). Each SBRIC in the network controls the self-testing of the elements in a separate one of the groups in sequence by broadcasting a test command to the elements in parallel which, in response, generate test signatures stored by the SBRIC. The SBRICs in the network are coupled in series in daisy chain fashion to enable the test signatures stored by the SBRICs to be concatenated for easy retrieval by shifting out the test signatures therefrom, using a technique such as boundary scan.

    NETWORK ADAPTOR CONNECTED TO A COMPUTER FOR VIRUS SIGNATURE RECOGNITION IN ALL FILES ON A NETWORK
    154.
    发明授权
    NETWORK ADAPTOR CONNECTED TO A COMPUTER FOR VIRUS SIGNATURE RECOGNITION IN ALL FILES ON A NETWORK 失效
    随着相关NETZADAPTORSCHALTUNG在所有的网络文件的病毒特征码检测的计算机。

    公开(公告)号:EP0638184B1

    公开(公告)日:1997-12-10

    申请号:EP93909808.3

    申请日:1993-04-28

    CPC classification number: H04L63/145 G06F21/564 G06F2201/83

    Abstract: A data processing system comprising a plurality of computers interconnected through a local network, preferably in the form of a ring. The network being connected to a network adapter which is able to receive all information on the network. The network adaptor is connected to a computer which together with the adaptor can perform an assembling and scanning of substantially all files on the network and carry out a recognition of virus signatures. The individual file packets circulation in the network are assembled, said file packets being assembled in a file and scanned for virus signatures. When a virus signature is detected in the file, information is simultaneously provided on the transmitting stations and the receiving stations, whereafter it is possible to transmit the vaccine to the stations in question.

    APPARATUS AND METHOD FOR TESTING INTEGRATED CIRCUITS
    156.
    发明公开
    APPARATUS AND METHOD FOR TESTING INTEGRATED CIRCUITS 失效
    DEVICE AND METHOD FOR测试集成电路

    公开(公告)号:EP0737337A1

    公开(公告)日:1996-10-16

    申请号:EP95904200.0

    申请日:1994-12-02

    Inventor: NEEDHAM, Wayne

    CPC classification number: G06F11/2236 G01R31/3183 G06F2201/83

    Abstract: A testing methodology for very large scale integrated circuits, for example, microprocessors having several million transistors. Initially a set of pseudorandom test patterns is selected. During the design of the integrated circuit it is partitioned into functional units and each unit is designed to be verified and tested by the test patterns. During a test mode all of the units of the integrated circuit receives the test patterns in parallel. The output from each unit is coupled to a signature register. The contents of the signature registers are examined following application of the test pattern. This testing methodology lends itself to the simultaneous testing of many integrated circuits.

    System and method for testing a programmable logic
    157.
    发明公开
    System and method for testing a programmable logic 失效
    用于测试可编程逻辑的系统和方法

    公开(公告)号:EP0584917A3

    公开(公告)日:1996-08-07

    申请号:EP93305406.6

    申请日:1993-07-09

    Abstract: The present invention provides a system and method for self-testing and self-checking programmable logic. According to the preferred embodiment, a system is provided which includes a multiplexer having an output coupled to the input of programmable logic, and inputs coupled to normal input signal sources and a pseudo-random number generator. The multiplexer selectively couples an input to its output responsive to an input source signal. The output of the programmable logic is applied to normal output components and a data compression register which is controlled by a read enable signal. The system further includes a configuration control which independently generates the input select signal and the read enable signal.

    Built-in self-test network
    159.
    发明公开
    Built-in self-test network 失效
    Netzwerk mit eingebautem Selbsttest。

    公开(公告)号:EP0568239A2

    公开(公告)日:1993-11-03

    申请号:EP93303024.9

    申请日:1993-04-20

    Applicant: AT&T Corp.

    CPC classification number: G01R31/318536 G01R31/318533 G06F2201/83

    Abstract: Control of the self-testing of a plurality of elements (12 1 - 12 m ), each having a Built-In, Self-Test (BIST) capability, and arranged in one or more groups (14 1 - 14 n ), is carried out by a network (16) of one or more standard BIST resource interface controllers (SBRICs 18 1 - 18 n ). Each SBRIC in the network controls the self-testing of the elements in a separate one of the groups in sequence by broadcasting a test command to the elements in parallel which, in response, generate test signatures stored by the SBRIC. The SBRICs in the network are coupled in series in daisy chain fashion to enable the test signatures stored by the SBRICs to be concatenated for easy retrieval by shifting out the test signatures therefrom, using a technique such as boundary scan.

    Abstract translation: 通过一个或多个组(141-14n)来控制多个元件(121-12m)的自检,每个元件(121-12m)具有内置,自检(BIST)能力并且被布置在一个或多个组中(141-14n) 一个或多个标准BIST资源接口控制器(SBRIC 181-187)的网络(16)。 网络中的每个SBRIC通过向并行的元素广播测试命令来顺序地控制单独的一个组中的元素的自检,其响应地生成由SBRIC存储的测试签名。 网络中的SBRIC以菊花链方式串联耦合,以使得SBRIC存储的测试签名能够通过使用诸如边界扫描的技术从其移出测试签名来简单地检索。

    Fehlertolerantes Datenverarbeitungssystem
    160.
    发明公开
    Fehlertolerantes Datenverarbeitungssystem 失效
    容错数据处理系统

    公开(公告)号:EP0246218A3

    公开(公告)日:1989-09-06

    申请号:EP87890089.3

    申请日:1987-05-07

    Abstract: Ein fehlertolerantes Datenverarbeitungssystem weist Gruppen (TMR) von gleiche binäre Datensignale liefernden und verarbei­tenden Rechnereinheiten (SRU) und je eine logische Entscheidungs­einheit (Voter) auf, welche über die Datensignale der Gruppe (TMR) abstimmt. Hiebei ist eine Mehrzahl von Gruppen (TMR) mit wenigstens drei, Datensignale liefernden oder verarbeitenden Rechnereinheiten (SRU) miteinander über Datenkanäle (K1, K2, K3) verbunden und die Voter einer Gruppe sind mit den Votern anderer Gruppen über Daten- bzw. Signalleitungen verbunden. Jede Daten­signale liefernde oder verarbeitende Rechnereinheit (SRU) kann wenigstens einen Voter für die Entscheidung über die Fehlerfrei­heit von Eingangs- und/oder Ausgangssignalen aufweisen. Zweck­mäßig enthält jede Datensignale liefernde oder verarbeitende Rechnereinheit (SRU) einen Sequenzvoter für die Entscheidung über die korrekte Reihenfolge der zu verarbeitenden Signale.

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