公开(公告)号：EP2577667A2

公开(公告)日：2013-04-10

申请号：EP11790301.3

申请日：2011-05-31

Applicant: Altera Corporation

Inventor： FUNG, Ryan ,  FENDER, Joshua David

IPC: G11C7/10 ,  G11C7/22 ,  H03K19/173

CPC classification number: G11C7/222 ,  G11C7/1036 ,  G11C7/1078 ,  G11C7/1093

Abstract: An apparatus includes an interface circuit coupled to an electronic device. The interface circuit provides source synchronous communication with the electronic device using a strobe signal. The interface circuit is configured to gate the strobe signal in order to successfully communicate with the electronic device.

公开(公告)号：EP1681680B1

公开(公告)日：2008-12-24

申请号：EP05077828.1

申请日：2002-09-17

Applicant: SanDisk Corporation

Inventor： Cernea, Paul Adrian

IPC: G11C7/10

CPC classification number: G11C7/1048 ,  G11C7/1036 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1078 ,  G11C7/1087

公开(公告)号：EP1997112A1

公开(公告)日：2008-12-03

申请号：EP06725144.7

申请日：2006-03-17

Applicant: Telefonaktiebolaget LM Ericsson (publ)

Inventor： RUTHEMANN, Klaus

IPC: G11C29/02 ,  G11C7/10 ,  G11C8/06

CPC classification number: G11C7/1036 ,  G11C7/22 ,  G11C7/222 ,  G11C8/06 ,  G11C29/003 ,  G11C29/02

Abstract: An apparatus for adjustment of a digital delay function of a data memory unit comprising said data memory unit (102), an elastic store register, ESR, (104) and read clock and write clock adapted to control read and write operations, a write counter associated with the write clock and a read counter associated with the read clock. Said memory (102) works in series with said ESR (104). The memory (102) delivers two data elements from two logically neighbouring cells. Said ESR (104) writes the two data elements from the memory (102) at every cycle of the write clock, wherein if the write counter is increased by one at a cycle of the write clock the output position in the memory (102) is not changed, and if the write counter is increased by two at one cycle of the write clock the output position in the memory (102) is moved backward by one data element and if the write counter is not changed at one cycle of the write clock the output position in the memory (102) is moved forward by one data element.

公开(公告)号：EP1428220B1

公开(公告)日：2006-07-05

申请号：EP02773439.1

申请日：2002-09-17

Applicant: SanDisk Corporation

Inventor： CERNEA, Raul Adrian

IPC: G11C7/10

CPC classification number: G11C7/1048 ,  G11C7/1036 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1078 ,  G11C7/1087

Abstract: Selecting circuits for columns of an array of memory cells are used to hold read data or write data of the memory cells. The memory cells may be multistate memory cells. There is a shift register chain, having a stage for columns of the array. A strobe pulse is shifted through this shift register. The strobe points, with each clock, at and enables a different selecting circuit in sequence. That particular selecting circuit that has been enabled by the strobe will then perform a certain function. In a read mode, the selected selecting circuit will send the stored information through to the output buffer for output from the integrated circuit. And while in a programming mode, the selected selecting circuit will receive data from an input buffer. This data will be written into a memory cell.

公开(公告)号：EP1543523A1

公开(公告)日：2005-06-22

申请号：EP03754648.8

申请日：2003-09-17

Applicant: SanDisk Corporation

Inventor： CERNEA, Raul-Adrian

IPC: G11C7/10 ,  G11C19/28

CPC classification number: G11C19/00 ,  G11C7/1036 ,  G11C16/10 ,  G11C16/26 ,  G11C2211/5642

Abstract: A non-volatile memory device capable of reading and writing a large number of memory cells in parallel has an architecture that reduces redundancy in the multiple read/write circuits to a minimum. In one aspect, data latches associated with the multiple read/write circuits are I/O enabled and coupled in a compact manner for storage and serial transfer. They are implemented by one or more chain of link modules, which can selectively behave as inverters or latches. A method enables the use of a minimum number of link modules by cycling data between a set of master link modules and a substantially smaller set of slave link modules.

公开(公告)号：EP1288956A2

公开(公告)日：2003-03-05

申请号：EP02023417.5

申请日：1999-02-10

Applicant: Lexmark International, Inc.

Inventor： Gibson, Bruce David ,  Parish, George Keith

IPC: G11C8/00

CPC classification number: B41J2/17546 ,  B41J2/04541 ,  B41J2/04563 ,  B41J2/0458 ,  B41J2/17526 ,  B41J25/34 ,  B41J2202/17 ,  G11C7/1036 ,  G11C8/10

Abstract: A memory device for storing and outputting information includes a plurality of memory matrices, each memory matrix containing a plurality of transistors having a drain, a source, and a gate and the plurality of transistors are arranged in a plurality of levels that proceed from a lowest to a highest level. A plurality of single bit shift registers is also provided for producing a serial output, each shift register having a memory input and an associated memory matrix, wherein the memory input of each shift register is electrically connected to the sources of the transistors in the highest level of the shift register's associated memory matrix. A plurality of address lines for receiving a decode signal function, a load signal, and a clock as well as an output line for transmitting the serial output of the plurality of shift registers is also provided. Embodiments of the invention may employ any number of shift registers and memory matrices independent of the number of available address lines.

Abstract translation: 一种用于存储和输出信息的存储器件包括多个存储器矩阵，每个存储器矩阵包含具有漏极，源极和栅极的多个晶体管，并且所述多个晶体管以从最低层 达到最高水平。 还提供多个单位移位寄存器用于产生串行输出，每个移位寄存器具有存储器输入和相关联的存储器矩阵，其中每个移位寄存器的存储器输入端以最高电平电连接到晶体管的源极 的移位寄存器的相关存储矩阵。 还提供了用于接收解码信号功能，负载信号和时钟的多个地址线以及用于传送多个移位寄存器的串行输出的输出线。 本发明的实施例可以采用与可用地址线的数量无关的任何数量的移位寄存器和存储器矩阵。

公开(公告)号：EP0862333A2

公开(公告)日：1998-09-02

申请号：EP98105936.3

申请日：1992-10-31

Applicant: General Instrument Corporation

Inventor： Shen, Paul ,  Paik, Woo H. ,  Krause, Edward A.

IPC: H04N7/50

CPC classification number: G11C7/1075 ,  G11C7/1036 ,  H04N19/423 ,  H04N19/433 ,  H04N19/51 ,  H04N19/61

Abstract: A multiple serial access memory is provided. A dynamic random access memory (30) is addressed to input data thereto and output data therefrom. Rows of data are output from the array (50) in response to address signals (34, 36, 38) provided thereto. A plurality of serial output ports (44, 46, 48) is coupled to the output of the array for selectively latching different rows of data output from the array. The serial output ports (44, 46, 48) are clocked to output the latched data therefrom. In an illustrated embodiment, each of the serial output ports contains a shift register (62, 64, 66, ... 68) having a length equal to the width of the memory array (30). The shift register is responsive to a first timing signal (42, 52) for latching a row of data from the array (30). A second timing signal actuates the shift register to shift a row of latched data. A serial access selector (70) coupled to the shift register outputs a selected portion of the shifted data from the serial output port. The memory has particular application as the frame store for a motion compensated interframe image coding/decoding system.

Abstract translation: 提供多个串行存取存储器。 动态随机存取存储器（30）被寻址以输入数据并从其输出数据。 响应于提供给它的地址信号（34,36,38），从阵列（50）输出数据行。 多个串行输出端口（44,46,48）耦合到阵列的输出端，用于选择性地锁存从阵列输出的不同数据行。 串行输出端口（44,46,48）被计时以从其输出锁存的数据。 在所示实施例中，每个串行输出端口包含具有等于存储器阵列（30）的宽度的长度的移位寄存器（62,64,66，... 68）。 移位寄存器响应于第一定时信号（42,42），用于锁存来自阵列（30）的一行数据。 第二定时信号启动移位寄存器以移位一行锁存数据。 耦合到移位寄存器的串行访问选择器（70）从串行输出端口输出移位数据的选定部分。 存储器具有特定的应用程序作为运动补偿帧间图像编码/解码系统的帧存储器。

公开(公告)号：EP0249985B1

公开(公告)日：1993-09-08

申请号：EP87108801.9

申请日：1987-06-19

Applicant: SONY CORPORATION

Inventor： Ebihara, Norio ,  Sasaki, Takayuki ,  Kita, Hiroyuki ,  Ohsawa, Yoshihito

IPC: H04N5/907

CPC classification number: G11C7/1036 ,  H04N5/907 ,  H04N9/877

公开(公告)号：EP0178922B1

公开(公告)日：1990-06-13

申请号：EP85307459.9

申请日：1985-10-16

Applicant: FUJITSU LIMITED

Inventor： Ogawa, Junji

IPC: G11C8/00 ,  G11C7/00

CPC classification number: G11C7/1036 ,  G11C7/1006 ,  G11C11/4096

公开(公告)号：EP0249985A3

公开(公告)日：1989-08-23

申请号：EP87108801.9

申请日：1987-06-19

Applicant: SONY CORPORATION

Inventor： Ebihara, Norio ,  Sasaki, Takayuki ,  Kita, Hiroyuki ,  Ohsawa, Yoshihito

IPC: H04N5/907

CPC classification number: G11C7/1036 ,  H04N5/907 ,  H04N9/877

Abstract: A video memory, for use with a video tape recorder, a television receiver of the like to process a picture, is simplified and can achieve the functions of a time base corrector, a noise reduced and a comb filter, so as to considerably improve the quality of a video picture. A frequency converting circuit for use with the video memory includes a comparator (30) for comparing first and second address signals and an address correction circuit (38) connected to receive an output signal from the com­parator (30). When a crossing occurs between the first and second address signals, the sequential order in which an address signal is supplied to the memory (12) is switched by the address correcting circuit (38), to thereby derive a continuous output signal from the memory (12).