公开(公告)号：US07082286B2

公开(公告)日：2006-07-25

申请号：US10412475

申请日：2003-04-11

Applicant: John David Kaewell, Jr. ,  Timothy Berghuis ,  Jan Meyer ,  Peter Bohnhoff ,  Alexander Reznik ,  Edward L. Hepler ,  Michael Koch ,  William C. Hackett ,  David S. Bass ,  Steven Ferrante

Inventor： John David Kaewell, Jr. ,  Timothy Berghuis ,  Jan Meyer ,  Peter Bohnhoff ,  Alexander Reznik ,  Edward L. Hepler ,  Michael Koch ,  William C. Hackett ,  David S. Bass ,  Steven Ferrante

IPC: H04B15/00

CPC classification number: H04B1/7093 ,  H04B1/7075 ,  H04B1/7077 ,  H04B1/709 ,  H04B1/7113 ,  H04B1/7117 ,  H04B1/712 ,  H04B7/0491 ,  H04B2201/7071 ,  H04B2201/70711

Abstract: A Node-B/base station has a path searcher and at least one antenna for receiving signals from users. The path searcher comprises a set of correlators. Each correlator correlates an inputted user code with an inputted antenna output of the at least one antenna. An antenna controller selectively couples any output of the at least one antenna to an input of each correlator of the set of correlators. A code phase controller selects a user code for input into the set of correlators. Each delay of a series of delays delays the selected user code by a predetermined amount and each correlator of the set of correlators receives a different code phase delay of the selected user code. A sorter and path selector sorts the output energy levels of each correlator of the sets of correlators and produces a path profile for a user based on the sorted output energy levels.

Abstract translation: 节点B /基站具有路径搜索器和用于从用户接收信号的至少一个天线。 路径搜索器包括一组相关器。 每个相关器将输入的用户代码与至少一个天线的输入的天线输出相关联。 天线控制器选择性地将至少一个天线的任何输出耦合到该组相关器的每个相关器的输入端。 代码相位控制器选择用于输入到该组相关器的用户代码。 一系列延迟的每个延迟将所选择的用户码延迟预定量，并且该组相关器的每个相关器接收所选用户码的不同码相位延迟。 分拣机和路径选择器对相关器组的每个相关器的输出能量进行排序，并且基于排序的输出能级产生用户的路径简档。

公开(公告)号：US20060104389A1

公开(公告)日：2006-05-18

申请号：US11317524

申请日：2005-12-22

Applicant: Ravi Subramanian

Inventor： Ravi Subramanian

IPC: H04L27/06 ,  H04B1/10

CPC classification number: H04B1/0003 ,  H04B1/0007 ,  H04B1/28 ,  H04B1/406 ,  H04B1/70735 ,  H04B1/7085 ,  H04B2201/70701 ,  H04B2201/70711 ,  H04L25/0204

Abstract: A configurable all-digital coherent demodulator system for spread spectrum digital communications is disclosed herein. The demodulator system includes an extended and long-code demodulator (ELCD) coupled to a traffic channel demodulator (TCD) and a parameter estimator (PE). The demodulator also includes a pilot assisted correction device (PACD) that is coupled to the PE and the TCD. The ELCD provides a code-demodulated signal to the TCD and the PE. In turn, the TCD provides a demodulated output data signal to the PE. The PACD corrects the phase error of the demodulated output data based on an error estimate that is fed forward from the PE. Accumulation operations in the ELCD, TCD, and PE are all programmable. Similarly, a phase delay in the PACD is also programmable to provide synchronization with the error estimate from the PE.

Abstract translation: 本文公开了一种用于扩频数字通信的可配置全数字相干解调器系统。 解调器系统包括耦合到业务信道解调器（TCD）和参数估计器（PE）的扩展和长码解调器（ELCD）。 解调器还包括耦合到PE和TCD的导频辅助校正装置（PACD）。 ELCD向TCD和PE提供码解调信号。 反过来，TCD向PE提供解调的输出数据信号。 基于从PE馈送的误差估计，PACD校正解调输出数据的相位误差。 ELCD，TCD和PE中的累加操作都可编程。 类似地，PACD中的相位延迟也是可编程的，以提供与来自PE的误差估计的同步。

公开(公告)号：US07039134B1

公开(公告)日：2006-05-02

申请号：US10050968

申请日：2002-01-22

Applicant: Yaniv Avital ,  Ehud Reshef

Inventor： Yaniv Avital ,  Ehud Reshef

IPC: H04L27/06

CPC classification number: H04B1/707 ,  H04B1/7095 ,  H04B1/7115 ,  H04B2201/70711

Abstract: A reduced complexity correlator that enables the re-use of the most complex portions of a correlator, namely the multiplier and adder. The correlator of the present invention is especially well-suited for use in CDMA and W-CDMA spread spectrum communication systems that require the use of numerous correlators in their operation. Multiple input samples, multiple codes and integration results are stored in shift registers and circularly shifted and clocked out at appropriate clock rates such that the multiplication and accumulation steps of the correlation process are synchronized.

Abstract translation: 一种降低的复杂度相关器，其能够重新使用相关器的最复杂部分，即乘法器和加法器。 本发明的相关器特别适用于需要在其操作中使用大量相关器的CDMA和W-CDMA扩频通信系统。 多个输入样本，多个代码和积分结果存储在移位寄存器中，并以适当的时钟速率循环移位和计时，使得相关处理的乘法和累加步骤同步。

公开(公告)号：US20060013286A1

公开(公告)日：2006-01-19

申请号：US11179356

申请日：2005-07-11

Applicant: Ravi Subramanian

Inventor： Ravi Subramanian

IPC: H04B1/707

CPC classification number: H04B1/707 ,  H04B2201/70711

Abstract: A configurable multimode despreader for spread spectrum applications is disclosed herein. The despreader includes a plurality of data lines, at least one selective coupler coupled to the plurality of data lines, at least one multiplier coupled to the selective coupler, and a code input line coupled to the multiplier. The selective coupler selectively couples one of the plurality of data lines with the multiplier per any one of a plurality of despreading protocols. The multiplier then multiplies a desired input data type received from the selective coupler with a despreading code chip received from the code input line to produce an observation. The programmable multimode despreader supports variable code and data modulation schemes and variable spreading factors.

Abstract translation: 本文公开了一种用于扩频应用的可配置多模解扩器。 解扩器包括多个数据线，耦合到多个数据线的至少一个选择耦合器，耦合到选择耦合器的至少一个乘法器，以及耦合到乘法器的代码输入线。 所述选择性耦合器根据多个解扩协议中的任何一个选择性地将所述多条数据线中的一条与乘法器相耦合。 然后，乘法器将从选择耦合器接收的期望输入数据类型与从代码输入行接收到的解扩码芯片相乘以产生观察。 可编程多模解扩器支持可变码和数据调制方案和可变扩频因子。

公开(公告)号：US20050282534A1

公开(公告)日：2005-12-22

申请号：US11198692

申请日：2005-08-05

Applicant: Ravi Subramanian ,  Uma Jha ,  Joel Medlock

Inventor： Ravi Subramanian ,  Uma Jha ,  Joel Medlock

IPC: H04B1/707 ,  H04M3/00

CPC classification number: H04B1/0003 ,  H04B1/707 ,  H04B2201/7071 ,  H04B2201/70711

Abstract: A wireless spread spectrum communication platform for processing a communication signal is disclosed herein. The wireless communication platform includes a first computing element, a second computing element, and a reconfigurable interconnect. The first computing element is coupled to the second computing element via the reconfigurable interconnect. A design configuration of the first computing element is heterogeneous with respect to a design configuration of the second computing element. The reconfigurable interconnect has an uncommitted architecture, thereby allowing it to be configured by an outside source to couple portions of the first reconfigurable interconnect with portions of the second reconfigurable interconnect in a variety of combinations. The first computing element, the second computing element, and the reconfigurable interconnect operable to perform discrete functions suitable for processing of the communication signal.

Abstract translation: 本文公开了一种用于处理通信信号的无线扩频通信平台。 无线通信平台包括第一计算元件，第二计算元件和可重构互连。 第一计算元件经由可重构互连耦合到第二计算元件。 关于第二计算元件的设计配置，第一计算元件的设计配置是异构的。 可重配置互连具有未提交的架构，从而允许其由外部源配置以将第一可重配置互连的部分以各种组合耦合第二可重配置互连的部分。 第一计算元件，第二计算元件和可重构互连可操作以执行适于处理通信信号的离散功能。

公开(公告)号：US06934319B2

公开(公告)日：2005-08-23

申请号：US09751785

申请日：2000-12-29

Applicant: Ravi Subramanian

Inventor： Ravi Subramanian

IPC: H04B1/707 ,  H04L27/30

CPC classification number: H04B1/707 ,  H04B2201/70711

Abstract: A configurable multimode despreader for spread spectrum applications is disclosed herein. The despreader includes a plurality of data lines, at least one selective coupler coupled to the plurality of data lines, at least one multiplier coupled to the selective coupler, and a code input line coupled to the multiplier. The selective coupler selectively couples one of the plurality of data lines with the multiplier per any one of a plurality of despreading protocols. The multiplier then multiplies a desired input data type received from the selective coupler with a despreading code chip received from the code input line to produce an observation. The programmable multimode despreader supports variable code and data modulation schemes and variable spreading factors.

Abstract translation: 本文公开了一种用于扩频应用的可配置多模解扩器。 解扩器包括多个数据线，耦合到多个数据线的至少一个选择耦合器，耦合到选择耦合器的至少一个乘法器，以及耦合到乘法器的代码输入线。 所述选择性耦合器根据多个解扩协议中的任何一个选择性地将所述多条数据线中的一条与乘法器相耦合。 然后，乘法器将从选择耦合器接收的期望输入数据类型与从代码输入行接收到的解扩码芯片相乘以产生观察。 可编程多模解扩器支持可变码和数据调制方案和可变扩频因子。

公开(公告)号：US20040077352A1

公开(公告)日：2004-04-22

申请号：US10684650

申请日：2003-10-14

Inventor： Ronald L. Mahany

IPC: H04Q007/20

CPC classification number: H04W52/46 ,  H04B1/406 ,  H04B1/692 ,  H04B2201/70711 ,  H04W52/38

Abstract: A data transceiver module for digital data communications in a portable hand-held data terminal has multiple data spread spectrum modes which include direct sequence and frequency function modulation algorithms. The transceiver module has multiple user or program configurable data rates, modulation, channelization and process gain in order to maximize the performance of radio data transmissions and to maximize interference immunity. Various module housings, which may be PCMCIA type, are able to be mated with a suitably designed data terminal. Media access control protocols and interfaces of multiple nominal operational frequencies are utilized. Wireless access devices in a cell based network each consider a variety of factors when choosing one of a plurality of modes of wireless operation and associated operating parameters. Such selection defines a communication channel to support wireless data, message and communication exchanges. In further embodiments, the wireless access devices also support a second channel, a busy/control channel, for managing communication on the main communication channel and to overcome roaming and hidden terminal problems. Roaming terminal devices are also configured to support the dual channel design. Such configuration in both circumstances may involve the use of a multimode radio that is timeshared between the two channels or two radios, one dedicated to each channel.

公开(公告)号：US20040008640A1

公开(公告)日：2004-01-15

申请号：US10067496

申请日：2002-02-04

Applicant: QuickSilver Technology, Inc.

Inventor： Ghobad Heidari ,  Kuor-Hsin Chang

IPC: H04B007/216

CPC classification number: G06F15/7867 ,  H04B1/708 ,  H04B2201/70711

Abstract: A system for implementing a searcher for use with a communication device is provided. According to one aspect of the system, the searcher includes one or more computational units which are used to perform a PN sequence generation function to generate a sequence of PN codes. The searcher further includes a number of computational units which are used to correlate received signal samples with the PN codes. As each signal sample is received by the communication device, the received signal sample is correlated with a first PN sequence in a parallel manner using the computational units. The correlation results are then accumulated. As the next signal sample is received, this newly received signal sample is similarly correlated with the next PN sequence in a parallel manner. Likewise, the correlation results are accumulated with the previous correlation results. The foregoing process is repeated until all the signal samples needed for correlation are received and correlated with sequences of PN codes. According to another aspect of the system, the a computational units are implemented using adaptive hardware resources. The number of computational units which are used to implement the correlation function is adjustable depending on, for example, the amount of available adaptive hardware resources.

Abstract translation: 提供了一种用于实现与通信设备一起使用的搜索器的系统。 根据该系统的一个方面，搜索器包括一个或多个计算单元，用于执行PN序列生成功能以产生PN码序列。 搜索器还包括多个计算单元，用于将接收到的信号采样与PN码相关联。 由于每个信号采样由通信设备接收，所以接收的信号样本使用计算单元并行地与第一PN序列相关。 然后累积相关结果。 当接收到下一个信号样本时，新接收的信号样本与下一个PN序列以并行方式类似地相关。 同样地，相关结果与先前的相关结果一起累积。 重复上述过程，直到接收到相关所需的所有信号样本并与PN码的序列相关联。 根据系统的另一方面，使用自适应硬件资源来实现计算单元。 用于实现相关函数的计算单元的数量可以根据例如可用的自适应硬件资源的量来调整。

公开(公告)号：US06611512B1

公开(公告)日：2003-08-26

申请号：US09262280

申请日：1999-03-04

Applicant: Geoffrey F. Burns

Inventor： Geoffrey F. Burns

IPC: H04J1300

CPC classification number: H04B1/707 ,  H04B1/7075 ,  H04B1/7093 ,  H04B2001/70706 ,  H04B2201/70711

Abstract: An apparatus and method of a shared correlator system for a code division, multiple access (CDMA) receiver employs scheduling of correlation operations with identification tags (ID-tags). The scheduling allows for shared vector generation and correlation operations between processing units by pipeline processing. The shared correlator schedules correlation operations requested by processing units, generates matched-filter PN vectors associated with the identification tags for the correlation operations, and provides correlation results for the correlation operations. Scheduling may be implemented with a control processor, scheduler and memory. The control processor determines the matched-filter PN vector information for a requested operation using the current state of a reference PN code sequence, and this information is stored as the ID-tag. The control processor stores the ID-tag at an address in memory associated with a slot of a periodic symbol schedule. A counter of the scheduler steps through each memory address to provide an ID-tag for each slot. The ID-tag allows the matched-filter PN vector information for a requested correlation operation to be provided to the vector generator and vector correlator to generate the matched-filter PN vector for the slot.

Abstract translation: 一种用于码分多址（CDMA）接收机的共享相关器系统的装置和方法，采用与识别标签（ID-标签）进行相关运算调度。 调度允许通过流水线处理处理单元之间的共享向量生成和相关操作。 共享相关器调度由处理单元请求的相关操作，生成与用于相关操作的识别标签相关联的匹配滤波器PN矢量，并提供相关操作的相关结果。 调度可以用控制处理器，调度器和存储器来实现。 控制处理器使用参考PN码序列的当前状态来确定用于所请求操作的匹配滤波器PN向量信息，并且该信息被存储为ID标签。 控制处理器将ID标签存储在与周期性符号调度的时隙相关联的存储器中的地址处。 调度器的计数器遍历每个存储器地址以为每个时隙提供ID标签。 ID标签允许将所请求的相关操作的匹配滤波器PN向量信息提供给向量生成器和向量相关器，以产生该时隙的匹配滤波器PN向量。

公开(公告)号：US20020159469A1

公开(公告)日：2002-10-31

申请号：US09926241

申请日：2001-09-28

Inventor： Takuya Arimura

IPC: H04B007/216

CPC classification number: H04J13/0077 ,  G11C7/22 ,  G11C8/12 ,  G11C19/00 ,  H04B1/707 ,  H04B1/7093 ,  H04B2201/70701 ,  H04B2201/70711

Abstract: The memory circuit of the present invention temporarily stores information symbols included in a reception signal according to a CDMA system which allows multi-code communication to carry out coherent detection using a pilot symbol. The memory circuit of the present invention is constructed of a plurality of electrically independent memory blocks. Each memory block corresponds to one code and one slot of an information symbol. Write access and read access to memory blocks are generated periodically on condition that write access and read access to one memory block do not occur simultaneously. Blocks to which no access is generated are forcibly set to a low power consumption mode to reduce power consumption caused by accesses.

Abstract translation: 本发明的存储器电路根据允许多码通信的CDMA系统临时存储包括在接收信号中的信息符号，以使用导频符号进行相干检测。 本发明的存储电路由多个电独立的存储块构成。 每个存储器块对应于信息符号的一个代码和一个时隙。 在对一个存储块的写入访问和读取访问不会同时发生的条件下，周期性地生成对存储器块的写访问和读访问。 不生成访问的块被强制设置为低功耗模式，以减少由访问引起的功耗。