公开(公告)号：US20090311572A1

公开(公告)日：2009-12-17

申请号：US12159088

申请日：2006-12-27

Applicant: Mathieu Roy ,  Fabien Pierre

Inventor： Mathieu Roy ,  Fabien Pierre

IPC: H01M2/02 ,  H01M4/82

CPC classification number: H01M8/1097 ,  H01M8/0206 ,  H01M8/0232 ,  H01M8/04089 ,  H01M8/1004 ,  Y02P70/56 ,  Y10T29/49115

Abstract: A fuel cell having its active stack resting on a thin conductive layer, bearing on a wafer provided with through gas inlet channels, the thin conductive layer protruding in the active stack in front of each channel and being transparent to the gas.

Abstract translation: 一种燃料电池，其活性叠层位于薄导电层上，承载于设置有通过气体入口通道的晶片上，该薄导电层在每个通道的前方突出于有源堆叠中，并对气体透明。

公开(公告)号：US07634247B2

公开(公告)日：2009-12-15

申请号：US11664149

申请日：2005-03-15

Applicant: Loïc Joet ,  Daniel Saias ,  Eric Andre

Inventor： Loïc Joet ,  Daniel Saias ,  Eric Andre

IPC: H04B1/30

CPC classification number: H04B1/28 ,  H04B1/0025

Abstract: A method for sampling an analogue radiofrequency signal comprising reception of the analogue radiofrequency signal, sending of the received signal on two analogue channels, each channel performing a first signal sampling operation, including a filtering step eliminating signal frequencies that could fold on the useful signal during sampling such that the sampled signal represents a filtered version of the received signal, wherein the sampling frequency is taken to be equal to the frequency of the signal carrier divided by a factor Ndiv1+½, Ndiv1 being an integer number, to bring the useful signal to half of the sampling frequency after sampling.

Abstract translation: 一种对模拟射频信号进行采样的方法，包括接收模拟射频信号，在两个模拟信道上发送接收信号，每个信道执行第一信号采样操作，包括滤波步骤，消除可能在有用的信号上折叠的信号频率 信号，使得采样信号表示接收信号的滤波版本，其中采样频率取等于信号载波的频率除以因子Ndiv1 +½，Ndiv1为整数，以使得 有用的信号采样后采样频率的一半。

公开(公告)号：US07633851B2

公开(公告)日：2009-12-15

申请号：US10761708

申请日：2004-01-21

Applicant: Simone Mazzoni ,  Joel Cambonie

Inventor： Simone Mazzoni ,  Joel Cambonie

IPC: H04J11/00

CPC classification number: H04L27/2607 ,  H04L27/2628

Abstract: A circuit for generating a cyclic prefix of a symbol comprised of a sequence of time samples, the prefix being the reproduction of the last samples of the symbol at the beginning of the symbol, the symbol being obtained by inverse Fourier transform of complex coefficients corresponding to respective frequencies. The circuit includes a multiplier that shifts the phase of each complex coefficient by a value proportional to its frequency, a memory for storing the samples at the beginning of the symbol, and a multiplexer that copies at the end of the symbol the stored samples.

Abstract translation: 一种用于产生由时间序列序列构成的符号的循环前缀的电路，该前缀是在符号开始处的符号的最后样本的再现，该符号是通过对应于 各自的频率。 该电路包括乘法器，该乘法器将每个复系数的相位与其频率成比例的值移位，用于存储符号开始处的采样的存储器以及在符号结尾处复制存储的采样的多路复用器。

公开(公告)号：US07623837B2

公开(公告)日：2009-11-24

申请号：US11125291

申请日：2005-05-09

Applicant: Andreia Cathelin ,  Didier Belot

Inventor： Andreia Cathelin ,  Didier Belot

IPC: H04B1/10

CPC classification number: H03H7/0169 ,  H03H9/74 ,  H04B1/28

Abstract: A heterodyne receiving circuit for a digital communication system including a first band pass filter receiving a signal from an antenna, an amplifying circuit and a second narrow band pass filter for selecting one particular channel within a band of frequencies. The two filters are carried out with integrated BAW-type tunable resonators which can be adjusted, respectively, by a first electrical signal and a second electrical signal generated by two PLL-type frequency control loops. The second frequency control loop has a variable division factor for the purpose of selecting one particular channel within said band of frequencies. In addition, the receiving circuit includes a mixer for mixing the signal generated at the output of said second filter with a local oscillation frequency in order to produce an intermediate frequency. The division factor is controlled by a digital processing of the intermediate frequency.

Abstract translation: 一种用于数字通信系统的外差接收电路，包括接收来自天线的信号的第一带通滤波器，放大电路和用于选择频带内的一个特定信道的第二窄带通滤波器。 两个滤波器由集成的BAW型可调谐谐振器进行，分别可以通过由两个PLL型频率控制回路产生的第一电信号和第二电信号来调节。 第二频率控制回路具有可变分频因子，用于选择所述频带内的一个特定信道。 此外，接收电路包括用于将在所述第二滤波器的输出处产生的信号与本地振荡频率混合的混频器，以便产生中频。 分频因子由中频数字处理控制。

公开(公告)号：US07623405B2

公开(公告)日：2009-11-24

申请号：US12030463

申请日：2008-02-13

Applicant: Mark A. Lysinger ,  David C. McClure ,  François Jacquet

Inventor： Mark A. Lysinger ,  David C. McClure ,  François Jacquet

IPC: G11C5/14

CPC classification number: G11C5/143 ,  G11C11/412 ,  G11C11/413

Abstract: A circuit includes a memory cell having a high voltage supply node and a low voltage supply node. Power multiplexing circuitry is included to selectively apply one of a first set of voltages and a second set of voltages to the high and low voltage supply nodes of the cell in dependence upon a current operational mode of the cell. If the cell is in active read or write mode, then the multiplexing circuitry selectively applies the first set of voltages to the high and low voltage supply nodes. Conversely, if the cell is in standby no-read or no-write mode, then the multiplexing circuitry selectively applies the second set of voltages to the high and low voltage supply nodes. The second set of voltages are offset from the first set of voltages. More particularly, a low voltage in the second set of voltages is higher than a low voltage in the first set of voltages, and wherein a high voltage in the second set of voltages is less than a high voltage in the first set of voltages. The cell can be a member of an array of cells, in which case the selective application of voltages applies to the array depending on the active/standby mode of the array. The array can include a block or section within an overall memory device including many blocks or sections, in which case the selective application of voltages applies to individual blocks/sections depending on the active/standby mode of the block/section itself.

Abstract translation: 电路包括具有高电压供应节点和低电压供应节点的存储单元。 功率复用电路被包括以根据小区的当前操作模式来选择性地将第一组电压和第二组电压中的一个应用于小区的高电压和低电压供应节点。 如果单元处于活动读或写模式，则多路复用电路选择性地将第一组电压施加到高电压和低电压供应节点。 相反，如果单元处于待机无读或不写模式，则多路复用电路选择性地将第二组电压施加到高电压和低电压供应节点。 第二组电压偏离第一组电压。 更具体地，第二组电压中的低电压高于第一组电压中的低电压，并且其中第二组电压中的高电压小于第一组电压中的高电压。 单元可以是单元阵列的成员，在这种情况下，根据阵列的主动/待机模式，选择性地施加电压应用于阵列。 阵列可以包括包括许多块或部分在内的整个存储器件中的块或部分，在这种情况下，根据块/部分本身的主动/待机模式，选择性地施加电压施加到各个块/部分。

公开(公告)号：US07620868B2

公开(公告)日：2009-11-17

申请号：US11670553

申请日：2007-02-02

Applicant: Francois Tailliet ,  Laurent Murillo

Inventor： Francois Tailliet ,  Laurent Murillo

IPC: G06F11/00 ,  G01R31/28 ,  G06F7/38

CPC classification number: G01R31/318392 ,  G01R31/31703 ,  G01R31/31705 ,  G01R31/3177

Abstract: A method for detecting a malfunction in a state machine is described. The state machine has an operation modeled by a set of states linked to each other by transitions, the state machine generating, upon each transition, output signals according to input signals comprising signals generated during a previous transition. During a transition, the method comprises steps of generating at least one control signal according to a control signal generated during a previous transition, determining an expected value of the control signal, and comparing the control signal with the expected value.

Abstract translation: 描述了一种用于检测状态机故障的方法。 状态机具有由通过转换彼此链接的一组状态建模的操作，状态机根据包括在先前转换期间生成的信号的输入信号在每次转换时产生输出信号。 在转换期间，该方法包括以下步骤：根据在先前转换期间产生的控制信号产生至少一个控制信号，确定控制信号的期望值，以及将控制信号与期望值进行比较。

公开(公告)号：US07602878B2

公开(公告)日：2009-10-13

申请号：US12141798

申请日：2008-06-18

Applicant: Christophe Moreaux ,  Ahmed Kari ,  David Naura ,  Pierre Rizzo

Inventor： Christophe Moreaux ,  Ahmed Kari ,  David Naura ,  Pierre Rizzo

IPC: H03K21/00

CPC classification number: H03K23/66

Abstract: A binary frequency divider includes a counter paced by an input signal, means for comparing a counting value with first and second threshold values and supplying first and second control signals synchronized with variation edges of a first type of the input signal. The divider includes means for supplying at least one third control signal shifted by a half-period of the input signal in relation to one of the first or second control signals, and control means for generating the output signal using control signals chosen according to the value of at least one least significant bit of the division setpoint. Application is mainly but not exclusively to UHF transponders.

Abstract translation: 二进制分频器包括由输入信号起搏的计数器，用于将计数值与第一和第二阈值进行比较并提供与第一类型的输入信号的变化沿同步的第一和第二控制信号的装置。 分频器包括用于提供相对于第一或第二控制信号之一移位了输入信号的半周期的至少一个第三控制信号的装置，以及使用根据该值选择的控制信号产生输出信号的控制装置 的分区设定点的至少一个最低有效位。 应用主要但不仅限于UHF应答器。

公开(公告)号：US20090251235A1

公开(公告)日：2009-10-08

申请号：US12371415

申请日：2009-02-13

Applicant: Didier Belot ,  Alexandre Augusto Shirakawa ,  Eric Kerherve ,  Moustapha El Hassan ,  Yann Deval

Inventor： Didier Belot ,  Alexandre Augusto Shirakawa ,  Eric Kerherve ,  Moustapha El Hassan ,  Yann Deval

IPC: H03H9/02

CPC classification number: H03H9/605 ,  H03H9/542

Abstract: A filtering circuit with BAW type acoustic resonators having at least a first quadripole and a second quadripole connected in cascade, each quadripole having a branch series with a first acoustic resonator of type BAW and a branch parallel with each branch having an acoustic resonator of type BAW, the first acoustic resonator having a frequency of resonance series approximately equal to the frequency of parallel resonance of the second acoustic resonator, the branch parallel of the first quadripole having a first capacitance connected in series with the second resonator and, in parallel with the capacitance, a first switching transistor to short circuit the capacitance.

Abstract translation: 具有至少具有级联连接的第一四极和第二四极的BAW型声谐振器的滤波电路，每个四极具有与BAW类型的第一声谐振器的分支系列和与具有BAW型声谐振器的每个分支并联的分支 所述第一声谐振器具有大致等于所述第二声谐振器的并联谐振频率的共振频率，所述第一四极杆的分支并联具有与所述第二谐振器串联连接的第一电容器，并且与所述电容器 第一个开关晶体管使电容短路。

公开(公告)号：US07594119B2

公开(公告)日：2009-09-22

申请号：US10668795

申请日：2003-09-23

Applicant: Sophie Gabriele ,  William Orlando

Inventor： Sophie Gabriele ,  William Orlando

IPC: H04L9/00

CPC classification number: G06Q20/1235 ,  G06Q20/127 ,  G07F15/12 ,  G07F17/0014

Abstract: A system for detecting the time exceeding conditions of at least one application being executed by a processor, including: an element for storing time conditions, the conditions being sorted by increasing deadline order; a register for storing the condition closest to the current date; and a comparator of the deadline contained in the register with the current date of the system.

Abstract translation: 一种用于检测超过由处理器执行的至少一个应用的条件的时间的系统，包括：用于存储时间条件的元素，所述条件通过增加最终期限顺序排序; 用于存储最接近当前日期的条件的寄存器; 以及与该系统当前日期的登记册内的最后期限比较。

公开(公告)号：US07569889B2

公开(公告)日：2009-08-04

申请号：US11343920

申请日：2006-01-30

Applicant: François Jacquet

Inventor： François Jacquet

IPC: H01L29/76

CPC classification number: G11C11/419 ,  G11C7/02 ,  G11C7/18 ,  G11C2207/002

Abstract: A RAM memory integrated circuit, in particular a SRAM memory integrated circuit, includes a matrix of memory cells that are arranged between two bit lines via two access transistors. The bit lines are intended in one case to be discharged and in the other case to be maintained at a high precharge potential during a read operation. The bit line of each column of the matrix that is intended to be maintained at the high precharge potential is produced in the form of at least two partial bit lines. The memory cells of each column are implanted in the form of groups of cells which are alternately connected to one or the other of the partial bit lines, respectively.

Abstract translation: RAM存储器集成电路，特别是SRAM存储器集成电路，包括通过两个存取晶体管布置在两个位线之间的存储器单元矩阵。 在一种情况下，位线被放电，并且在另一种情况下在读取操作期间保持在高预充电电位。 旨在维持在高预充电电位的矩阵的每列的位线以至少两个部分位线的形式产生。 每列的存储单元以分别交替地连接到一个或另一个部分位线的单元组的形式注入。