公开(公告)号：JPS61264819A

公开(公告)日：1986-11-22

申请号：JP10935386

申请日：1986-05-12

Applicant: ADVANCED MICRO DEVICES INC

Inventor： BERUTORANDO JIEFUERII UIRIAMUZ

IPC: H03K19/013 ,  H03K19/0175 ,  H03K19/018

Abstract: A logic level translator (110) having a fast rising edge at its output for converging ECL logic levels into TTL logic levels includes a switching transistor (Q1) having its base adapted to receive an input logic level signal representative of an ECL signal, the collector of the switching transistor (Q1) being connected to an output node (4). A clamp delay circuit (D1, Q2, Rx, Cx) is interconnected between the collector and the base of the switching transistor (Q1) for inhibiting the switching transistor (Q1) from receiving feedback current to its base so as to cause a faster turn-off, thereby producing a fast rising edge response at the output node (4) during a high-to-low transition of the input logic level signal.

公开(公告)号：JPS61146041A

公开(公告)日：1986-07-03

申请号：JP28685785

申请日：1985-12-17

Applicant: ADVANCED MICRO DEVICES INC

Inventor： BEMIS GERALD L

IPC: H04L12/42 ,  H04L12/433 ,  H04L25/49

Abstract: A code conversion system is described for converting a stream of data between first and second data codes. The stream of data containing data packets is recognized to be subject to a data fault condition arising from the collision of data packets. The conversion system comprises means for detecting the fault condition, and means for altering the code conversion of the stream of data between the first and second codes so as to reflect the occurrence of the fault condition in the code converted stream of data.

公开(公告)号：JPS6190266A

公开(公告)日：1986-05-08

申请号：JP22111585

申请日：1985-10-02

Applicant: Advanced Micro Devices Inc

Inventor： BAANAADO JIEI YUU

IPC: G06F17/10 ,  G06F7/544 ,  G06F15/31

CPC classification number: G06F7/5443

公开(公告)号：JPS6186855A

公开(公告)日：1986-05-02

申请号：JP21443885

申请日：1985-09-26

Applicant: Advanced Micro Devices Inc

Inventor： OOMU PII AGURAWARU ,  JIYOUZEFU EI BURUSHITSUCHI

IPC: G06F13/12 ,  G06F13/10 ,  G06F15/78 ,  H03K19/173 ,  H03K19/177

CPC classification number: H03K19/17744 ,  H03K19/1733 ,  H03K19/17716

公开(公告)号：JPS6184854A

公开(公告)日：1986-04-30

申请号：JP21443585

申请日：1985-09-26

Applicant: Advanced Micro Devices Inc

Inventor： KIYANDEISU EICHI BURAUN

IPC: H01L23/50 ,  H01L21/50 ,  H01L21/56 ,  H01L21/60 ,  H01L23/28 ,  H01L23/31

CPC classification number: H01L24/80 ,  H01L21/56 ,  H01L23/3107 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/30105 ,  H01L2924/30107 ,  Y10T29/49169 ,  Y10T29/49172 ,  H01L2924/00

公开(公告)号：JPS6146510A

公开(公告)日：1986-03-06

申请号：JP17305985

申请日：1985-08-05

Applicant: Advanced Micro Devices Inc

Inventor： GIRU ESU RII ,  ASHIYOKU KUMAARU

IPC: H03K5/02 ,  G06F1/10 ,  H03K19/0175 ,  H03K19/018

CPC classification number: H03K19/01806

公开(公告)号：JPS60239796A

公开(公告)日：1985-11-28

申请号：JP9531785

申请日：1985-05-02

Applicant: ADVANCED MICRO DEVICES INC

Inventor： DINES STEVEN ,  SFARTI ADRIAN ,  DANIEL ANDREW DAVID

IPC: G06F3/153 ,  G09G1/16 ,  G09G5/00 ,  G09G5/20 ,  G09G5/39 ,  G09G5/393 ,  G09G5/395

公开(公告)号：JPS60230705A

公开(公告)日：1985-11-16

申请号：JP7631485

申请日：1985-04-09

Applicant: ADVANCED MICRO DEVICES INC

Inventor： MISHERGI AYOUB HADI ,  APFEL RUSSELL JAY ,  LANGE ARTHUR FRANCIS

IPC: H04Q1/45 ,  G06F1/02 ,  H03B28/00 ,  H03K4/02 ,  H03K4/94 ,  H04L27/26 ,  H04M1/50

公开(公告)号：JP2014116623A

公开(公告)日：2014-06-26

申请号：JP2014010604

申请日：2014-01-23

Applicant: Advanced Micro Devices Inc ,  アドバンスト・マイクロ・ディバイシズ・インコーポレイテッドAdvanced Micro Devices Incorporated

Inventor： RICHARD J CARTER ,  MICHAEL J HARGROVE ,  GEORGE J KLUTH ,  JOHN G PELLERIN

IPC: H01L21/8234 ,  H01L21/336 ,  H01L27/088 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L21/823456 ,  H01L21/28114 ,  H01L21/823468 ,  H01L29/4933 ,  H01L29/66545

Abstract: PROBLEM TO BE SOLVED: To provide a method for achieving a band end voltage threshold for both short and long channel devices.SOLUTION: A method is provided for manufacturing an integrated circuit including a short channel (SC) device 16 and a long channel (LC) device 18 each overlaid by an interlayer dielectric 75. The SC device 16 has an SC gate stack 34, and the LC device 18 initially has a dummy gate 50. In one embodiment, the method includes the steps of removing the dummy gate to form an LC device trench, and depositing metal gate material over the SC device 16 and the LC device 18. The metal gate material contacts the SC gate stack 34 and substantially fills the LC device trench.

Abstract translation: 要解决的问题：提供一种实现短通道和长通道器件的带宽电压阈值的方法。解决方案：提供一种制造集成电路的方法，该集成电路包括短沟道（SC）器件16和长沟道（LC） ）器件18，其每个由层间电介质75覆盖.SC器件16具有SC栅极堆叠34，并且LC器件18最初具有伪栅极50.在一个实施例中，该方法包括以下步骤：去除伪栅极以形成 LC器件沟槽，以及在SC器件16和LC器件18上沉积金属栅极材料。金属栅极材料接触SC栅极叠层34并基本上填充LC器件沟槽。

公开(公告)号：JP2009288818A

公开(公告)日：2009-12-10

申请号：JP2009211488

申请日：2009-09-14

Applicant: Advanced Micro Devices Inc ,  アドバンスト・マイクロ・ディバイシズ・インコーポレイテッドAdvanced Micro Devices Incorporated

Inventor： LUKANC TODD P ,  SPENCE CHRISTOPHER A

IPC: G03F1/34 ,  G03F1/00 ,  G03F1/26 ,  G03F1/30 ,  G03F1/36

CPC classification number: G03F1/30 ,  G03F1/36 ,  G03F1/70

Abstract: PROBLEM TO BE SOLVED: To generate phase shifting patterns to improve patterning of gates and other layers, structures or regions needing sub-nominal dimensions.
SOLUTION: A technique is disclosed, in which a first boundary region is added to the ends of a phase zero (0) pattern defining polygons and a second boundary region is added to the ends of a phase 180 pattern. This technique can improve the line-end pattern definition and improve the manufacturability and a patterning process window. The added boundary region balances the light on both sides of the line ends, resulting in a more predictable final resist pattern.
COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：产生相移模式以改善栅极和其他层，需要亚标称尺寸的结构或区域的图案化。 解决方案：公开了一种技术，其中第一边界区域被添加到限定多边形的相位零（0）图案的端部，并且第二边界区域被添加到相位180图案的端部。 这种技术可以改善线端图案定义并提高可制造性和图案化工艺窗口。 添加的边界区域平衡线末端的两侧的光，导致更可预测的最终抗蚀剂图案。 版权所有（C）2010，JPO＆INPIT