公开(公告)号：US11222782B2

公开(公告)日：2022-01-11

申请号：US16785491

申请日：2020-02-07

Applicant: Microchip Technology Inc.

Inventor： Amaury Gendron-Hansen ,  Bruce Odekirk

IPC: H01L21/02 ,  H01L21/04 ,  H01L27/092 ,  H01L21/67

Abstract: A method for fabricating a silicon carbide semiconductor device includes providing a SiC epitaxial layer disposed over a surface of a SiC substrate, forming an implant aperture in a hardmask layer on a surface of the expitaxial SiC layer, implanting contact and well regions in the SiC epitaxial layer through the hardmask layer, the contact region lying completely within and recessed from edges of the well region by performing one of implanting the well region through the implant aperture, reducing the area of the implant aperture forming a reduced-area contact implant aperture and implanting the contact region through the reduced-area implant aperture to form a contact region, and implanting the contact region through the implant aperture, increasing the area of the implant aperture to form a increased-area well implant aperture and implanting the well region through the increased-area implant aperture to form a well region completely surrounding the contact region.

公开(公告)号：US20210211267A1

公开(公告)日：2021-07-08

申请号：US16827624

申请日：2020-03-23

Applicant: Microchip Technology Inc.

Inventor： Thomas JOERGENSEN ,  Brian BRANSCOMB

IPC: H04L7/00 ,  H04L12/931

Abstract: A PHY chip for a synchronous Ethernet system includes N network input/output (I/O) ports, a first external recovered clock input, a first recovered clock output, and a first clock multiplexer having a plurality of data inputs, a select input, and an output coupled to the first recovered clock output, at least one of the data inputs coupled to a first recovered clock from a respective one of the N network I/O ports, a first additional data input coupled to the first external recovered clock input.

公开(公告)号：US10972249B1

公开(公告)日：2021-04-06

申请号：US17022480

申请日：2020-09-16

Applicant: Microchip Technology Inc.

Inventor： Peter John Waldemar Graumann

IPC: H04L7/00 ,  H04L25/03

Abstract: A system and method for data sampler drift compensation in a SerDes receiver. Off-data values are received at a drift compensation engine from a plurality of data value selectors coupled to one of a plurality of data sampler pairs of a speculative Decision Feedback Equalizer (DFE) of a SerDes receiver. A drift compensation value for each of the data samplers is generated by the drift compensation engine based upon the off-data values received from each of the plurality of data value selectors and, a sampling level of each of the data samplers of the plurality of data sampler pairs of the DFE is adjusted based upon the drift compensation value from the drift compensation engine.

公开(公告)号：US10972084B1

公开(公告)日：2021-04-06

申请号：US16867468

申请日：2020-05-05

Applicant: Microchip Technology Inc.

Inventor： Michael R. Williamson

IPC: H03K5/135 ,  H03K5/00

Abstract: A circuit for transferring a n-bit phase value between circuits includes a system clock input, a n-bit phase value generator coupled to the system clock input generating a phase value output, and an edge output indicating the phase output value is valid, a latching clock delay circuit having an input coupled to the system clock input, an input coupled to the edge output, a variable phase delay circuit coupled to the phase value output, a delay adder having a first input coupled to the phase value output, a second input coupled to a delay offset signal, and an output coupled to the control input of the variable phase delay circuit, and a phase flip-flop having a data input coupled to the output of the variable phase delay circuit, a clock input coupled to a latching clock output of the variable output clock delay circuit and a Phase Out output.

公开(公告)号：US10819318B1

公开(公告)日：2020-10-27

申请号：US16595096

申请日：2019-10-07

Applicant: Microchip Technology Inc.

Inventor： Barry Britton ,  Phillip Johnson ,  John Schadt ,  David Onimus

IPC: H03K3/356 ,  H03K3/037 ,  G11C11/4078 ,  H03K19/003 ,  G06F1/14 ,  H03K5/133

Abstract: An SEU immune flip-flop includes a master stage data latch having an input, an output, a clock input, being transparent in response to a clock signal first state and being latched in response to a clock signal second state, a slave stage data latch having an input coupled to the master stage data latch output, an output, a scan output, a slave latch clock input, a scan slave latch having an input coupled to the slave stage data latch scan output, an output, and a clock input, being transparent in response to the clock signal second state and being latched in response to the clock signal first state. The slave stage data latch includes a switched inverter disabled when the slave latch is in a transparent state and enabled when the slave latch is in a latched state having a time delay longer than an SEU time period.

公开(公告)号：US20200327937A1

公开(公告)日：2020-10-15

申请号：US16405895

申请日：2019-05-07

Applicant: Microchip Technology Inc.

Inventor： Victor Nguyen ,  Fethi Dhaoui ,  John L. McCollum ,  Fengliang Xue

IPC: G11C13/00 ,  H01L45/00

Abstract: A ReRAM memory cell includes a ReRAM device including a solid electrolyte layer disposed between a first ion-source electrode and a second electrode and a select circuit including two series-connected select transistors connected in series with the ReRAM device, each of the two series-connected select transistors having a gate connected to a separate control line.

公开(公告)号：US09621149B2

公开(公告)日：2017-04-11

申请号：US14817107

申请日：2015-08-03

Applicant: Microchip Technology Inc.

Inventor： Benedict C. K. Choy ,  James T. Walker ,  Ming-Yuan Yeh

IPC: H03K17/16 ,  H03K17/06

CPC classification number: H03K17/063 ,  H03K17/163

Abstract: Systems and methods are disclosed for operating a highly linearized resistance for a switch through use of a bootstrapped features. In one exemplary implementation, there is provided a method and system that implements a method for operating a circuit configured to provide a highly linearized resistance including receiving a signal via a bootstrapped switch, coupling the received signal to a gate if the received signal is high, receiving a signal via a switch control input coupled to a high impedance element. Moreover, the method includes coupling the high impedance element to the gate and turning off the switch via a gate turn off when the gate turn off pulls the gate low.

公开(公告)号：US09474118B2

公开(公告)日：2016-10-18

申请号：US14549433

申请日：2014-11-20

Applicant: Microchip Technology Inc.

Inventor： Alexander Mednik

IPC: H05B33/08

CPC classification number: H05B33/0845 ,  H05B33/0815 ,  H05B33/0818 ,  Y02B20/346

Abstract: The invention comprises a dimming switch for use with a string of light emitting diodes (LEDs). The dimming switch comprises a bipolar junction transistor (BJT) driven in a cascode scheme. The dimming switch also comprises circuitry to offset the current that drives the base of the BJT to provide a controlled amount of current to the LEDs when the dimming input signal is high.

Abstract translation: 本发明包括用于一串发光二极管（LED）的调光开关。 调光开关包括以共源共享方案驱动的双极结型晶体管（BJT）。 调光开关还包括用于抵消驱动BJT的基极的电流的电路，以在调光输入信号为高时向LED提供受控量的电流。

公开(公告)号：US09265103B2

公开(公告)日：2016-02-16

申请号：US14680010

申请日：2015-04-06

Applicant: Microchip Technology Inc.

Inventor： Scott Lynch ,  Benedict C. K. Choy

IPC: H05B33/08

CPC classification number: H05B33/0812 ,  H05B33/0815 ,  H05B33/0818 ,  H05B33/0827 ,  H05B33/083 ,  H05B33/0845 ,  Y02B20/347

Abstract: An LED driver circuit for controlling direct current supplied to a plurality of serially connected segments of Light Emitting Diodes (LEDs) is disclosed. In one embodiment, the LED driver circuit comprises a self-commutating circuit, which comprises a plurality of current control elements, each current control element having two ends, a first end connected to a different end of each segment along the plurality of serially connected segments of LEDs and a second end connected to a path to ground. The path to ground comprises a sense resistor and the path to ground is shared by the second end of each current control element. Each current control element is coupled to an adjacent current control element by a cross-regulation circuit and controlled by a signal from an adjacent current control element.

公开(公告)号：US20150369854A1

公开(公告)日：2015-12-24

申请号：US14743945

申请日：2015-06-18

Applicant: Microchip Technology Inc.

Inventor： ALEXANDER MEDNIK ,  ROHIT TIRUMALA ,  MARK TAN ,  SIMON KRUGLY

IPC: G01R31/26 ,  G01R31/02

CPC classification number: G01R31/2621 ,  G01R31/025 ,  H02H3/044 ,  H02H3/08 ,  H02H3/093

Abstract: A circuit and method are provided detecting a persistent short circuit in a power MOSFET for the purpose of protecting a load from over-current.

Abstract translation: 提供了检测功率MOSFET中的持续短路以便保护负载免受过电流的电路和方法。